Layouts for the Shuffle-exchange Graph and Lower Bound Techniques for VLSI
| dc.contributor.advisor | Miller, Gary L. | en_US |
| dc.contributor.author | Leighton, Frank Thomson | en_US |
| dc.date.accessioned | 2023-03-29T15:06:33Z | |
| dc.date.available | 2023-03-29T15:06:33Z | |
| dc.date.issued | 1982-08 | |
| dc.identifier.uri | https://hdl.handle.net/1721.1/149552 | |
| dc.description.abstract | The thesis is divided into two parts. In the first part, we describe and analyze several new VLSI layouts for the shuffle-exchange graph. These include:1) an asymptotically optimal, (N /log N)-area layout for the N-node shuffle-exchange graph, and 2) several practical layouts for small shuffle-exchange graphs. | en_US |
| dc.relation.ispartofseries | MIT-LCS-TR-274 | |
| dc.title | Layouts for the Shuffle-exchange Graph and Lower Bound Techniques for VLSI | en_US |
| dc.identifier.oclc | 19873567 | |
| dc.identifier.oclc | 9479447 |
