Compaction with Automatic Job Introduction
| dc.contributor.advisor | Leiserson, Charles E. | en_US |
| dc.contributor.author | Maley, F. Miller | en_US |
| dc.date.accessioned | 2023-03-29T15:13:54Z | |
| dc.date.available | 2023-03-29T15:13:54Z | |
| dc.date.issued | 1986-11 | |
| dc.identifier.uri | https://hdl.handle.net/1721.1/149639 | |
| dc.description.abstract | This thesis presents an algorithm for one-dimensional compaction of VLSI layouts. It differs from older methods in treating wires not as objects to be moved, but as constraints on the positions of other circuit components. These constraints are determined for each wiring layer using the theory of planar routing. | en_US |
| dc.relation.ispartofseries | MIT-LCS-TR-372 | |
| dc.title | Compaction with Automatic Job Introduction | en_US |
| dc.identifier.oclc | 16963144 |
