MACE: A Multiprocessing Approach to Circuit Extraction
| dc.contributor.author | Levitin, Samuel M. | en_US |
| dc.contributor.author | Terman, Christopher J. | en_US |
| dc.contributor.author | Slater, Kenneth H. | en_US |
| dc.date.accessioned | 2023-03-29T15:14:13Z | |
| dc.date.available | 2023-03-29T15:14:13Z | |
| dc.date.issued | 1986-10 | |
| dc.identifier.uri | https://hdl.handle.net/1721.1/149644 | |
| dc.description.abstract | The ever-increasing complexity of VLSI chips threaten to choke out all available computer power unless methods are devised to keep the CAD tasks conveniently sized. A review of the current methods of multiprocessing approaches in the domain of layout verification precedes the discussion of current work. | en_US |
| dc.relation.ispartofseries | MIT-LCS-TR-378 | |
| dc.title | MACE: A Multiprocessing Approach to Circuit Extraction | en_US |
| dc.identifier.oclc | 16952733 |
