Synthesis of Self-timed VLSI Circuits from Graph-theoretic Specifications
| dc.contributor.advisor | Dennis, Jack B. | en_US |
| dc.contributor.author | Chu, Tam-Anh | en_US |
| dc.date.accessioned | 2023-03-29T15:14:55Z | |
| dc.date.available | 2023-03-29T15:14:55Z | |
| dc.date.issued | 1987-06 | |
| dc.identifier.uri | https://hdl.handle.net/1721.1/149657 | |
| dc.description.abstract | This thesis presents an approach for direct and efficient synthesis of self-timed (asynchronous) control circuits from formal specifications called Signal Transition Graphs (STGs). Control circuits synthesized from this graph model are speed-independent and capable of performing concurrent operation. | en_US |
| dc.relation.ispartofseries | MIT-LCS-TR-393 | |
| dc.title | Synthesis of Self-timed VLSI Circuits from Graph-theoretic Specifications | en_US |
| dc.identifier.oclc | 18431813 |
