Design and Implementation of a Packet Switched Routing Chip
| dc.contributor.author | Joerg, Christopher Frank | en_US |
| dc.date.accessioned | 2023-03-29T15:16:58Z | |
| dc.date.available | 2023-03-29T15:16:58Z | |
| dc.date.issued | 1990-12 | |
| dc.identifier.uri | https://hdl.handle.net/1721.1/149693 | |
| dc.description.abstract | Monsoon is a parallel processing dataflow computer that will require a high bandwidth interconnection network. A packet switched routing chip (PaRC) is described that will be used as the basis of this network. PaRC is a 4 by 4 routing switch which has been designed and fabricated as a CMOS gate array. | en_US |
| dc.relation.ispartofseries | MIT-LCS-TR-482 | |
| dc.title | Design and Implementation of a Packet Switched Routing Chip | en_US |
| dc.identifier.oclc | 23126764 |
