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dc.contributor.advisorAgarwal, Ananten_US
dc.contributor.authorChaiken, David Larsen_US
dc.date.accessioned2023-03-29T15:17:24Z
dc.date.available2023-03-29T15:17:24Z
dc.date.issued1990-09
dc.identifier.urihttps://hdl.handle.net/1721.1/149698
dc.description.abstractCaches have the potential to provide multiprocessors with an automatic mechanism for reducing both network traffic and average memory access latency. However, cache-based systems must address the problem of cache coherence.en_US
dc.relation.ispartofseriesMIT-LCS-TR-489
dc.titleCache Coherence Protocols for Large-Scale Multiprocessorsen_US
dc.identifier.oclc22601242


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