A Timing Analysis and Optimization System for Level-clocked Circuitry
| dc.contributor.advisor | Leiserson, Charles E. | en_US |
| dc.contributor.author | Papaefthymiou, Marios Christos | en_US |
| dc.date.accessioned | 2023-03-29T15:22:07Z | |
| dc.date.available | 2023-03-29T15:22:07Z | |
| dc.date.issued | 1993-09 | |
| dc.identifier.uri | https://hdl.handle.net/1721.1/149766 | |
| dc.description.abstract | This thesis investigates timing analysis and optimization issues in synchronous circuitry. The major thrust of our work is a collection of provably correct and efficient algorithms that perform a variety of architectural-level operations on level-clocked | en_US |
| dc.relation.ispartofseries | MIT-LCS-TR-605 | |
| dc.title | A Timing Analysis and Optimization System for Level-clocked Circuitry | en_US |
