Spatula: A Hardware Accelerator for Sparse Matrix Factorization
Author(s)
Feldmann, Axel; Sanchez, Daniel
Download3613424.3623783.pdf (1.682Mb)
Publisher with Creative Commons License
Publisher with Creative Commons License
Creative Commons Attribution
Terms of use
Metadata
Show full item recordAbstract
Solving sparse systems of linear equations is a crucial component in many science and engineering problems, like simulating physical systems. Sparse matrix factorization dominates a large class of these solvers. Efficient factorization algorithms have two key properties that make them challenging for existing architectures: they consist of small tasks that are structured and compute-intensive, and sparsity induces long chains of data dependences among these tasks. Data dependences make GPUs struggle, while CPUs and prior sparse linear algebra accelerators also suffer from low compute throughput.
We present Spatula, an architecture for accelerating sparse matrix factorization algorithms. Spatula hardware combines systolic processing elements that execute structured tasks at high throughput with a flexible scheduler that handles challenging data dependences. Spatula enables a novel scheduling algorithm that avoids stalls and load imbalance while reducing data movement, achieving high compute utilization. As a result, Spatula outperforms a GPU running the state-of-the-art sparse Cholesky and LU factorization implementations by gmean 47 × across a wide range of matrices, and by up to thousands of times on some challenging matrices.
Date issued
2023-10-28Department
Massachusetts Institute of Technology. Computer Science and Artificial Intelligence LaboratoryPublisher
ACM|56th Annual IEEE/ACM International Symposium on Microarchitecture
Citation
Feldmann, Axel and Sanchez, Daniel. 2023. "Spatula: A Hardware Accelerator for Sparse Matrix Factorization."
Version: Final published version
ISBN
979-8-4007-0329-4
Collections
The following license files are associated with this item: