dc.contributor.author | Williams, R. Ryan | |
dc.date.accessioned | 2024-07-12T15:55:53Z | |
dc.date.available | 2024-07-12T15:55:53Z | |
dc.date.issued | 2024-06-10 | |
dc.identifier.isbn | 979-8-4007-0383-6 | |
dc.identifier.uri | https://hdl.handle.net/1721.1/155669 | |
dc.description | STOC ’24, June 24–28, 2024, Vancouver, BC, Canada | en_US |
dc.description.abstract | Many results in fine-grained complexity reveal intriguing consequences from solving various SAT problems even slightly faster than exhaustive search. We prove a “self-improving” (or “bootstrapping”) theorem for Circuit-SAT, #Circuit-SAT, and its fully-quantified version: solving one of these problems faster for “large” circuit sizes implies a significant speed-up for “smaller” circuit sizes. Our general arguments work for a variety of models solving circuit-analysis problems, including non-uniform circuits and randomized models of computation.
We derive striking consequences for the complexities of these problems, in both the fine-grained and parameterized setting. For example, we show that certain fine-grained improvements on the runtime exponents of polynomial-time versions of Circuit-SAT would imply subexponential-time algorithms for Circuit-SAT on 2o(n)-size circuits, refuting the Exponential Time Hypothesis. We also show that any algorithm for Circuit-SAT with k inputs and n gates running in 1000000k + n1+ε time (for all ε > 0) would imply algorithms running in time (1+ε)k + n1+ε time (for all ε > 0), also refuting the Exponential Time Hypothesis. Applying our ideas in the #Circuit-SAT setting, we prove new unconditional lower bounds against uniform circuits with symmetric gates for functions in deterministic linear time. | en_US |
dc.publisher | ACM | en_US |
dc.relation.isversionof | 10.1145/3618260.3649723 | en_US |
dc.rights | Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use. | en_US |
dc.source | Association for Computing Machinery | en_US |
dc.title | Self-Improvement for Circuit-Analysis Problems | en_US |
dc.type | Article | en_US |
dc.identifier.citation | Williams, R. Ryan. 2024. "Self-Improvement for Circuit-Analysis Problems." | |
dc.contributor.department | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science | |
dc.identifier.mitlicense | PUBLISHER_POLICY | |
dc.eprint.version | Final published version | en_US |
dc.type.uri | http://purl.org/eprint/type/ConferencePaper | en_US |
eprint.status | http://purl.org/eprint/status/NonPeerReviewed | en_US |
dc.date.updated | 2024-07-01T07:50:57Z | |
dc.language.rfc3066 | en | |
dc.rights.holder | The author(s) | |
dspace.date.submission | 2024-07-01T07:50:57Z | |
mit.license | PUBLISHER_POLICY | |
mit.metadata.status | Authority Work and Publication Information Needed | en_US |