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dc.contributor.authorLau, Stella
dc.contributor.authorBourgeat, Thomas
dc.contributor.authorPit-Claudel, Cl?ment
dc.contributor.authorChlipala, Adam
dc.date.accessioned2025-01-28T14:06:49Z
dc.date.available2025-01-28T14:06:49Z
dc.date.issued2024-12-02
dc.identifier.isbn979-8-4007-0636-3
dc.identifier.urihttps://hdl.handle.net/1721.1/158084
dc.descriptionCCS ’24, October 14–18, 2024, Salt Lake City, UT, USA.en_US
dc.description.abstractThe process isolation enforceable by commodity hardware and operating systems is too weak to protect secrets from malicious code running on the same machine: attacks exploit timing side channels derived from contention on shared microarchitectural resources to extract secrets. With appropriate hardware support, however, we can construct isolated enclaves and safeguard independent processes from interference through timing side channels, a step towards confidentiality and integrity guarantees. In this paper, we describe our work on formally specifying and verifying that a synthesizable hardware architecture implements strong timing isolation for enclaves. We reason about the cycle-accurate semantics of circuits with respect to a trustworthy formulation of strong isolation based on "air-gapped machines" and develop a modular proof strategy that sidesteps the need to prove functional correctness of processors. We apply our method on a synthesizable, multicore, pipelined RISC-V design formalized in Coq.en_US
dc.publisherACM|Proceedings of the 2024 ACM SIGSAC Conference on Computer and Communications Securityen_US
dc.relation.isversionofhttps://doi.org/10.1145/3658644.3690203en_US
dc.rightsCreative Commons Attributionen_US
dc.rights.urihttps://creativecommons.org/licenses/by/4.0/en_US
dc.sourceAssociation for Computing Machineryen_US
dc.titleSpecification and Verification of Strong Timing Isolation of Hardware Enclavesen_US
dc.typeArticleen_US
dc.identifier.citationLau, Stella, Bourgeat, Thomas, Pit-Claudel, Cl?ment and Chlipala, Adam. 2024. "Specification and Verification of Strong Timing Isolation of Hardware Enclaves."
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Scienceen_US
dc.identifier.mitlicensePUBLISHER_CC
dc.eprint.versionFinal published versionen_US
dc.type.urihttp://purl.org/eprint/type/ConferencePaperen_US
eprint.statushttp://purl.org/eprint/status/NonPeerRevieweden_US
dc.date.updated2025-01-01T08:49:07Z
dc.language.rfc3066en
dc.rights.holderThe author(s)
dspace.date.submission2025-01-01T08:49:07Z
mit.licensePUBLISHER_CC
mit.metadata.statusAuthority Work and Publication Information Neededen_US


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