Self-aligned fabrication of vertical, fin-based structures

Abstract

Modern power devices rely on complex, three-dimensional, vertical designs to increase their power density, ease their thermal management, and improve their reliability. However, fabrication techniques have historically relied on 2D processes for patterning lateral features. This work presents a new technology that uses multiple steps of angled depositions to fabricate self-aligned vertical, fin-based devices that avoid fundamental lithography resolution and alignment limitations. The fabrication flows of two devices, the self-aligned vertical finFET and the high-κ dielectric fin diode, are presented to demonstrate how angled depositions can readily achieve transistors with submicrometer, vertical gates in a source-first process and also create high-aspect ratio GaN fins with a record 70:1 aspect ratio.