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dc.contributor.authorCho, Myong Hyon
dc.contributor.authorLis, Mieszko
dc.contributor.authorShim, Keun Sup
dc.contributor.authorKinsy, Michel A.
dc.contributor.authorDevadas, Srinivas
dc.date.accessioned2010-02-25T14:55:18Z
dc.date.available2010-02-25T14:55:18Z
dc.date.issued2009
dc.date.submitted2009-12
dc.identifier.isbn978-1-60558-774-5
dc.identifier.urihttp://hdl.handle.net/1721.1/51826
dc.description.abstractPath-based, Randomized, Oblivious, Minimal routing (PROM) is a family of oblivious, minimal, path-diverse routing algorithms especially suitable for Network-on-Chip applications with n x n mesh geometry. Rather than choosing among all possible paths at the source node, PROM algorithms achieve the same effect progressively through efficient, local randomized decisions at each hop. Routing is deadlock-free in all PROM algorithms when the routers have at least two virtual channels. While the approach we present can be viewed as a generalization of both ROMM and O1TURN routing, it combines the low-hardware cost of O1TURN with the routing diversity offered by the most complex n-phase ROMM schemes. As all PROM algorithms employ the same hardware, a wide range of routing behaviors, from O1TURN-equivalent to uniformly path-diverse, can be effected by adjusting just one parameter, even while the network is live and continues to forward packets. Detailed simulation on a set of benchmarks indicates that, on equivalent hardware, the performance of PROM algorithms compares favorably to existing oblivious routing algorithms, including dimension-ordered routing, two-phase ROMM, and O1TURN.en
dc.language.isoen_US
dc.publisherAssociation for Computing Machineryen
dc.relation.isversionofhttp://doi.acm.org/10.1145/1645213.1645220en
dc.rightsAttribution-Noncommercial-Share Alike 3.0 Unporteden
dc.rights.urihttp://creativecommons.org/licenses/by-nc-sa/3.0/en
dc.sourceauthor/dept web pageen
dc.titlePath-Based, Randomized, Oblivious, Minimal Routingen
dc.typeArticleen
dc.identifier.citationCho, Myong Hyon et al. “Path-based, randomized, oblivious, minimal routing.” Proceedings of the 2nd International Workshop on Network on Chip Architectures. New York, New York: ACM, 2009. 23-28.en
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Scienceen_US
dc.contributor.approverDevadas, Srinivas
dc.contributor.mitauthorCho, Myong Hyon
dc.contributor.mitauthorLis, Mieszko
dc.contributor.mitauthorShim, Keun Sup
dc.contributor.mitauthorKinsy, Michel A.
dc.contributor.mitauthorDevadas, Srinivas
dc.relation.journalProceedings of the 2nd International Workshop on Network on Chip Architecturesen
dc.eprint.versionAuthor's final manuscript
dc.type.urihttp://purl.org/eprint/type/SubmittedJournalArticleen
eprint.statushttp://purl.org/eprint/status/PeerRevieweden
dspace.orderedauthorsCho, Myong Hyon; Lis, Mieszko; Shim, Keun Sup; Kinsy, Michel; Devadas, Srinivasen
dc.identifier.orcidhttps://orcid.org/0000-0001-8253-7714
dc.identifier.orcidhttps://orcid.org/0000-0003-4301-1159
dspace.mitauthor.errortrue
mit.licenseOPEN_ACCESS_POLICYen
mit.metadata.statusComplete


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