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BUILDING MANY-CORE PROCESSOR-TO-DRAM NETWORKS WITH MONOLITHIC CMOS SILICON PHOTONICS

dc.contributor.authorBatten, Christopher
dc.contributor.authorJoshi, Ajay J.
dc.contributor.authorOrcutt, Jason Scott
dc.contributor.authorKhilo, Anatol M.
dc.contributor.authorMoss, Benjamin Roy
dc.contributor.authorHolzwarth, Charles W.
dc.contributor.authorPopovic, Milos
dc.contributor.authorLi, Hanqing
dc.contributor.authorSmith, Henry Ignatius
dc.contributor.authorHoyt, Judy L.
dc.contributor.authorKaertner, Franz X.
dc.contributor.authorRam, Rajeev J.
dc.contributor.authorStojanovic, Vladimir Marko
dc.contributor.authorAsanovic, Krste
dc.date.accessioned2010-03-12T21:16:10Z
dc.date.available2010-03-12T21:16:10Z
dc.date.issued2009-07
dc.identifier.issn0272-1732
dc.identifier.urihttp://hdl.handle.net/1721.1/52556
dc.description.abstractSilicon photonics is a promising technology for addressing memory bandwidth limitations in future many-core processors. This article first introduces a new monolithic silicon-photonic technology, which uses a standard bulk CMOS process to reduce costs and improve energy efficiency, and then explores the logical and physical implications of leveraging this technology in processor-to-memory networks.en
dc.description.sponsorshipDARPA/MTO (award W911NF-06- 1-0449)en
dc.language.isoen_US
dc.publisherInstitute of Electrical and Electronics Engineersen
dc.relation.isversionofhttp://doi.ieeecomputersociety.org/10.1109/MM.2009.60en
dc.rightsArticle is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.en
dc.sourceIEEEen
dc.titleBUILDING MANY-CORE PROCESSOR-TO-DRAM NETWORKS WITH MONOLITHIC CMOS SILICON PHOTONICSen
dc.typeArticleen
dc.identifier.citationChristopher Batten, Ajay Joshi, Jason Orcutt, Anatol Khilo, Benjamin Moss, Charles W. Holzwarth, Miloš A. Popović, Hanqing Li, Henry I. Smith, Judy L. Hoyt, Franz X. Kärtner, Rajeev J. Ram, Vladimir Stojanović, Krste Asanović, "Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics," IEEE Micro, vol. 29, no. 4, pp. 8-21, July/Aug. 2009, doi:10.1109/MM.2009.60 © 2009 IEEEen
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Scienceen_US
dc.contributor.approverHoyt, Judy L.
dc.contributor.mitauthorBatten, Christopher
dc.contributor.mitauthorJoshi, Ajay J.
dc.contributor.mitauthorOrcutt, Jason Scott
dc.contributor.mitauthorKhilo, Anatol M.
dc.contributor.mitauthorMoss, Benjamin Roy
dc.contributor.mitauthorHolzwarth, Charles W.
dc.contributor.mitauthorPopovic, Milos
dc.contributor.mitauthorLi, Hanqing
dc.contributor.mitauthorSmith, Henry Ignatius
dc.contributor.mitauthorHoyt, Judy L.
dc.contributor.mitauthorKaertner, Franz X.
dc.contributor.mitauthorRam, Rajeev J.
dc.contributor.mitauthorStojanovic, Vladimir Marko
dc.relation.journalIEEE Microen
dc.eprint.versionFinal published versionen
dc.type.urihttp://purl.org/eprint/type/JournalArticleen
eprint.statushttp://purl.org/eprint/status/PeerRevieweden
dspace.orderedauthorsBatten, Christopher; Joshi, Ajay; Orcutt, Jason; Khilo, Anatol; Moss, Benjamin; Holzwarth, Charles W.; Popovic, Miloš A.; Li, Hanqing; Smith, Henry I.; Hoyt, Judy L.; Kartner, Franz X.; Ram, Rajeev J.; Stojanovic, Vladimir; Asanovic, Krsteen
dc.identifier.orcidhttps://orcid.org/0000-0002-0259-5541
dc.identifier.orcidhttps://orcid.org/0000-0001-8690-231X
dc.identifier.orcidhttps://orcid.org/0000-0002-8733-2555
dc.identifier.orcidhttps://orcid.org/0000-0003-0420-2235
dc.identifier.orcidhttps://orcid.org/0000-0002-8048-0678
mit.licensePUBLISHER_POLICYen
mit.metadata.statusComplete


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