dc.contributor.author | Brooks, Lane | |
dc.contributor.author | Lee, Hae-Seung | |
dc.date.accessioned | 2010-03-15T14:57:34Z | |
dc.date.available | 2010-03-15T14:57:34Z | |
dc.date.issued | 2009-12 | |
dc.date.submitted | 2009-08 | |
dc.identifier.issn | 0018-9200 | |
dc.identifier.uri | http://hdl.handle.net/1721.1/52575 | |
dc.description.abstract | Zero-crossing based switch capacitor circuits have been introduced as alternatives to op-amp based circuits for eased design considerations and improved power efficiency. This work further improves the resolution, power efficiency, and robustness of previous zero-crossing based circuits (ZCBCs) and features a 90 nm CMOS, offset compensated, fully differential, zero-crossing based, 12b, 50 MS/s, pipelined ADC requiring no CMFB. The power consumption is 4.5 mW. The FOM is 88 fJ/step. Fully differential signaling is used to improve power supply rejection and power efficiency. A power efficient chopping offset compensation technique is presented. Reference voltage switching is improved to avoid gate boosted switches. Redundancy is used to reduce output range requirements for increased signal range. Two regenerative latch architectures used for bit decision comparison are analyzed and measured for offset, noise, and speed. | en |
dc.description.sponsorship | Massachusetts Institute of Technology. Center for Integrated Circuits and Systems | en |
dc.description.sponsorship | National Defense Science and Engineering Graduate Fellowship | en |
dc.description.sponsorship | Defence Advanced Research Projects Agency (Grant N66001-06-2046) | en |
dc.language.iso | en_US | |
dc.publisher | Institute of Electrical and Electronics Engineers | en |
dc.relation.isversionof | http://dx.doi.org/10.1109/JSSC.2009.2032639 | en |
dc.rights | Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use. | en |
dc.source | IEEE | en |
dc.subject | zero-crossing based circuits | en |
dc.subject | scaled CMOS | en |
dc.subject | offset compensation | en |
dc.subject | comparator-based switched-capacitor circuits | en |
dc.subject | chopping | en |
dc.subject | chopper stabilization | en |
dc.subject | ZCBC | en |
dc.subject | CHS | en |
dc.subject | CBSC | en |
dc.subject | ADC | en |
dc.subject | A/D | en |
dc.title | A 12b, 50 MS/s, Fully Differential Zero-Crossing Based Pipelined ADC | en |
dc.type | Article | en |
dc.identifier.citation | Brooks, L., and Hae-Seung Lee. “A 12b, 50 MS/s, Fully Differential Zero-Crossing Based Pipelined ADC.” Solid-State Circuits, IEEE Journal of 44.12 (2009): 3329-3343. © 2009 IEEE | en |
dc.contributor.department | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science | |
dc.contributor.approver | Lee, Hae-Seung | |
dc.contributor.mitauthor | Brooks, Lane | |
dc.contributor.mitauthor | Lee, Hae-Seung | |
dc.relation.journal | IEEE Journal of Solid-State Circuits | en |
dc.eprint.version | Final published version | en |
dc.type.uri | http://purl.org/eprint/type/JournalArticle | en |
eprint.status | http://purl.org/eprint/status/PeerReviewed | en |
dspace.orderedauthors | Brooks, Lane; Lee, Hae-Seung | en |
dc.identifier.orcid | https://orcid.org/0000-0002-7783-0403 | |
mit.license | PUBLISHER_POLICY | en |
mit.metadata.status | Complete | |