Progress and challenges in the direct monolithic integration of III-V devices and Si CMOS on silicon substrates
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We present results on the direct monolithic integration of III-V devices and Si CMOS on a silicon substrate. Through optimization of device fabrication and material growth processes III-V devices with electrical performance comparable to devices grown on native III-V substrates were grown directly in windows adjacent to CMOS transistors on silicon template wafers or SOLES (Silicon on Lattices Engineered Substrates). While the results presented here are for InP HBTs, our direct heterogeneously integration approach is equally applicable to other III-V electronic (FETs, HEMTs) and opto-electronic (photodiodes, VSCLS) devices and opens the door to a new class of highly integrated, high performance, mixed signal circuits.
Date issued
2009-05Department
Massachusetts Institute of Technology. Department of Materials Science and EngineeringJournal
IEEE International Conference on Indium Phosphide & Related Materials, 2009. IPRM '09.
Publisher
Institute of Electrical and Electronics Engineers
Citation
Kazior, T.E. et al. “Progress and challenges in the direct monolithic integration of III–V devices and Si CMOS on silicon substrates.” Indium Phosphide & Related Materials, 2009. IPRM '09. IEEE International Conference on. 2009. 100-104. © 2009 IEEE
Version: Final published version
ISBN
978-1-4244-3432-9
ISSN
1092-8669
Keywords
Monolithic integrated circuits, Silicon, Indium Phosphide, Heterojunction bipolar transistors, CMOS integrated circuits