A modeling and exploration framework for interconnect network design in the nanometer Era
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As we approach serious scaling roadblocks in the next few process nodes, it is imperative to identify new emerging technologies that can complement or supplant CMOS in the future. We present an integrated cyclic approach to explore new interconnect technologies in the nanometer era for many core systems, where on-chip interconnects are jointly optimized at all the levels in the design hierarchy to develop a complete interconnect solution - from interconnect technology to network topology.
Date issued
2009-06Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer ScienceJournal
Proceedings of the 3rd ACM/IEEE International Symposium on Networks-on-Chip (NoCS 2009)
Publisher
Institute of Electrical and Electronics Engineers
Citation
Joshi, A., F. Chen, and V. Stojanovic. “A Modeling and exploration framework for interconnect network design in the nanometer era.” Networks-on-Chip, 2009. NoCS 2009. 3rd ACM/IEEE International Symposium on. 2009. 91. © 2009 IEEE
Version: Final published version
ISBN
978-1-4244-4142-6