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A 0.7-V 1.8-mW H.264/AVC 720p Video Decoder

Research and Teaching Output of the MIT Community

Show simple item record Finchelstein, Daniel Frederic Sze, Vivienne Sinangil, Mahmut Ersin Chandrakasan, Anantha P. 2010-06-02T15:37:37Z 2010-06-02T15:37:37Z 2009-10 2009-01
dc.identifier.issn 0018-9200
dc.identifier.other INSPEC Accession Number: 10957788
dc.description.abstract The H.264/AVC video coding standard can deliver high compression efficiency at a cost of increased complexity and power. The increasing popularity of video capture and playback on portable devices requires that the power of the video codec be kept to a minimum. This work implements several architecture optimizations such as increased parallelism, pipelining with FIFOs, multiple voltage/frequency domains, and custom voltage-scalable SRAMs that enable low voltage operation to reduce the power of a high-definition decoder. Dynamic voltage and frequency scaling can efficiently adapt to the varying workloads by leveraging the low voltage capabilities and domain partitioning of the decoder. An H.264/AVC Baseline Level 3.2 decoder ASIC was fabricated in 65-nm CMOS and verified. For high definition 720p video decoding at 30 frames per second (fps), it operates down to 0.7 V with a measured power of 1.8 mW, which is significantly lower than previously published results. The highly scalable decoder is capable of operating down to 0.5 V for decoding QCIF at 15 fps with a measured power of 29 muW. en
dc.description.sponsorship Texas Instruments Incorporated en
dc.description.sponsorship Nokia Corporation en
dc.language.iso en_US
dc.publisher Institute of Electrical and Electronics Engineers en
dc.relation.isversionof en
dc.rights Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use. en
dc.source IEEE en
dc.subject low-power electronics en
dc.subject cache memories en
dc.subject SRAM chips en
dc.subject Video codecs en
dc.subject H.264/AVC en
dc.subject CMOS memory circuits en
dc.subject CMOS digital integrated circuits en
dc.title A 0.7-V 1.8-mW H.264/AVC 720p Video Decoder en
dc.type Article en
dc.identifier.citation Sze, V. et al. “A 0.7-V 1.8-mW H.264/AVC 720p Video Decoder.” Solid-State Circuits, IEEE Journal of 44.11 (2009): 2943-2956. © 2009 Institute of Electrical and Electronics Engineers. en
dc.contributor.department Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science en_US
dc.contributor.department Massachusetts Institute of Technology. Microsystems Technology Laboratories en_US
dc.contributor.approver Chandrakasan, Anantha P.
dc.contributor.mitauthor Sze, Vivienne
dc.contributor.mitauthor Sinangil, Mahmut Ersin
dc.contributor.mitauthor Chandrakasan, Anantha P.
dc.relation.journal IEEE Journal of Solid-State Circuits en
dc.identifier.mitlicense PUBLISHER_POLICY en
dc.eprint.version Final published version en
dc.type.uri en
eprint.status en
dspace.orderedauthors Sze, Vivienne; Finchelstein, Daniel F.; Sinangil, Mahmut E.; Chandrakasan, Anantha P. en

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