Bounded Dataflow Networks and Latency-Insensitive Circuits
Author(s)Vijayaraghavan, Muralidaran; Arvind, Arvind
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We present a theory for modular refinement of Synchronous Sequential Circuits (SSMs) using Bounded Dataflow Networks (BDNs). We provide a procedure for implementing any SSM into an LI-BDN, a special class of BDNs with some good compositional properties. We show that the Latency-Insensitive property of LI-BDNs is preserved under parallel and iterative composition of LI-BDNs. Our theory permits one to make arbitrary cuts in an SSM and turn each of the parts into LI-BDNs without affecting the overall functionality. We can further refine each constituent LI-BDN into another LI-BDN which may take different number of cycles to compute. If the constituent LI-BDN is refined correctly we guarantee that the overall behavior would be cycle-accurate with respect to the original SSM. Thus one can replace, say a 3-ported register file in an SSM by a one-ported register file without affecting the correctness of the SSM. We give several examples to show how our theory supports a generalization of previous techniques for Latency-Insensitive refinements of SSMs.
DepartmentMassachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory; Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
7th IEEE/ACM International Conference on Formal Methods and Models for Co-Design, 2009. MEMOCODE '09.
Institute of Electrical and Electronics Engineers
Vijayaraghavan, Muralidaran, and Arvind. “Bounded Dataflow Networks and Latency-Insensitive circuits.” Formal Methods and Models for Co-Design, 2009. MEMOCODE '09. 7th IEEE/ACM International Conference on. 2009. 171-180. ©2009 Institute of Electrical and Electronics Engineers.
Final published version