dc.contributor.author | Li, Yan | |
dc.contributor.author | Stojanovic, Vladimir Marko | |
dc.date.accessioned | 2010-10-08T14:59:41Z | |
dc.date.available | 2010-10-08T14:59:41Z | |
dc.date.issued | 2009-08 | |
dc.date.submitted | 2009-07 | |
dc.identifier.isbn | 978-1-6055-8497-3 | |
dc.identifier.issn | 0738-100X | |
dc.identifier.other | INSPEC Accession Number: 10844460 | |
dc.identifier.uri | http://hdl.handle.net/1721.1/58966 | |
dc.description.abstract | This paper proposes an equation-based multi-scenario iterative robust
optimization methodology for analog/mixed-signal circuits.
We show that due to local circuit performance monotonicity in random
variations constraint maximization can be used to efficiently
find critical constraints and worst-case scenarios of random process
variations and populate them into a multi-scenario optimization.
This algorithm scales gracefully with circuit size and is tested on
both two-stage and fully differential folded-cascode operational amplifiers
with a 90 nm predictive model. The improving yield-trends
are confirmed across process and random variations with Hspice
Monte-Carlo simulations. | en_US |
dc.description.sponsorship | Massachusetts Institute of Technology. Center for Integrated Circuits and Systems | en_US |
dc.language.iso | en_US | |
dc.publisher | Institute of Electrical and Electronics Engineers | en_US |
dc.relation.isversionof | http://doi.acm.org/10.1145/1629911.1630065 | en_US |
dc.rights | Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use. | en_US |
dc.source | IEEE | en_US |
dc.subject | Algorithms | en_US |
dc.subject | Robust Circuit Optimization | en_US |
dc.subject | Variability | en_US |
dc.subject | Yield | en_US |
dc.subject | Analog Circuits | en_US |
dc.title | Yield-driven iterative robust circuit optimization algorithm | en_US |
dc.type | Article | en_US |
dc.identifier.citation | Yan Li; Stojanovic, V.; , "Yield-driven iterative robust circuit optimization algorithm," Design Automation Conference, 2009. DAC '09. 46th ACM/IEEE , vol., no., pp.599-604, 26-31 July 2009. Copyright 2009 ACM | en_US |
dc.contributor.department | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science | en_US |
dc.contributor.approver | Stojanovic, Vladimir Marko | |
dc.contributor.mitauthor | Li, Yan | |
dc.contributor.mitauthor | Stojanovic, Vladimir Marko | |
dc.relation.journal | Proceedings of the 46th ACM/IEEE Design Automation Conference, 2009 | en_US |
dc.eprint.version | Final published version | en_US |
dc.type.uri | http://purl.org/eprint/type/JournalArticle | en_US |
eprint.status | http://purl.org/eprint/status/PeerReviewed | en_US |
dspace.orderedauthors | Li, Yan; Stojanović, Vladimir | en |
mit.license | PUBLISHER_POLICY | en_US |
mit.metadata.status | Complete | |