A model for the critical voltage for electrical degradation of GaN high electron mobility transistors

Abstract

We have found that there is a critical drain-to-gate voltage beyond which GaN high-electron mobility transistors start to degrade in electrical-stress experiments. The critical voltage depends on the detailed voltage biasing of the device during electrical stress. It is higher in the OFF state and high-power state than at VDS = 0. In addition, as |VGS| increases, the critical voltage decreases. We have also found that the stress current does not affect the critical voltage although soft degradation at low voltages takes place at high stress currents. All of our findings are consistent with a degradation mechanism based on crystallographic-defect formation due to the inverse piezoelectric effect. Hot-electron-based mechanisms seem to be in contradiction with our experimental results.