dc.contributor.author | Kim, Byungsub | |
dc.contributor.author | Dickson, Timothy O. | |
dc.contributor.author | Liu, Yong | |
dc.contributor.author | Bulzacchelli, John F. | |
dc.contributor.author | Friedman, Daniel J. | |
dc.date.accessioned | 2010-11-05T18:54:39Z | |
dc.date.available | 2010-11-05T18:54:39Z | |
dc.date.issued | 2009-05 | |
dc.date.submitted | 2009-02 | |
dc.identifier.isbn | 978-1-4244-3458-9 | |
dc.identifier.other | INSPEC Accession Number: 10727922 | |
dc.identifier.uri | http://hdl.handle.net/1721.1/59837 | |
dc.description.abstract | The design of compact low-power I/O transceivers continues to be a challenge for both chip-to-chip and backplane applications. The introduction of dense fine-pitch silicon packaging technologies, that in principle are capable of supporting tens of thousands of high-data-rate I/O for local chip-to-chip interconnect, will make I/O area and power requirements even more stringent.This paper describes an alternative low-power compact I/O transceiver with RX equalization that achieves the required multi-bit postcursor cancellation without a high tap-count DFE. While this work targets data transmission over Si carrier links at rates up to 10Gb/s, it is also relevant to backplane channels. | en_US |
dc.language.iso | en_US | |
dc.publisher | Institute of Electrical and Electronics Engineers | en_US |
dc.relation.isversionof | http://dx.doi.org/10.1109/ISSCC.2009.4977368 | en_US |
dc.rights | Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use. | en_US |
dc.source | IEEE | en_US |
dc.title | A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS | en_US |
dc.type | Article | en_US |
dc.identifier.citation | Yong Liu et al. “A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS.” Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International. 2009. 182-183,183a. © 2009 Institute of Electrical and Electronics Engineers. | en_US |
dc.contributor.department | Massachusetts Institute of Technology. Research Laboratory of Electronics | en_US |
dc.contributor.approver | Kim, Byungsub | |
dc.contributor.mitauthor | Kim, Byungsub | |
dc.relation.journal | IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009 | en_US |
dc.eprint.version | Final published version | en_US |
dc.type.uri | http://purl.org/eprint/type/JournalArticle | en_US |
eprint.status | http://purl.org/eprint/status/PeerReviewed | en_US |
dspace.orderedauthors | Yong Liu; Byungsub Kim; Dickson, T.O.; Bulzacchelli, J.F.; Friedman, D.J. | en |
mit.license | PUBLISHER_POLICY | en_US |
mit.metadata.status | Complete | |