A single-slope 80MS/s ADC using two-step time-to-digital conversion

Abstract

An 80 MS/s analog-to-digital converter (ADC) based on single-slope conversion is presented which utilizes a recently developed gated ring oscillator (GRO) time-to-digital converter (TDC) to achieve an ENOB of 6.45 bits. To save power, the time-to-digital conversion is done in two steps, the first of which is based on coarse time quantization as measured by cycles of an oscillator and the second of which is based on fine time quantization by the GRO TDC. The resulting 0.13 mum CMOS prototype circuit is simple and compact in its implementation and consumes 6.4 mW of power.