A single-slope 80MS/s ADC using two-step time-to-digital conversion
DownloadPark-2009-A single-slope 80MSs ADC using two-step time-to-digital conversion.pdf (645.5Kb)
PUBLISHER_POLICY
Publisher Policy
Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
Terms of use
Metadata
Show full item recordAbstract
An 80 MS/s analog-to-digital converter (ADC) based on single-slope conversion is presented which utilizes a recently developed gated ring oscillator (GRO) time-to-digital converter (TDC) to achieve an ENOB of 6.45 bits. To save power, the time-to-digital conversion is done in two steps, the first of which is based on coarse time quantization as measured by cycles of an oscillator and the second of which is based on fine time quantization by the GRO TDC. The resulting 0.13 mum CMOS prototype circuit is simple and compact in its implementation and consumes 6.4 mW of power.
Date issued
2009-06Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer ScienceJournal
IEEE International Symposium on Circuits and Systems, 2009. ISCAS 2009
Publisher
Institute of Electrical and Electronics Engineers
Citation
Min Park, and M.H. Perrott. “A single-slope 80MS/s ADC using Two-Step Time-to-Digital Conversion.” Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on. 2009. 1125-1128. ©2009 IEEE.
Version: Final published version
Other identifiers
INSPEC Accession Number: 10761038
ISBN
978-1-4244-3827-3