Optimization of transistors for very high frequency dc-dc converters
Author(s)Perreault, David J.; Sagneri, Anthony D.; Anderson, David I.
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This document presents a method to optimize integrated LDMOS transistors for use in very high frequency (VHF, 30-300 MHz) dc-dc converters. A transistor model valid at VHF switching frequencies is developed. Device parameters are related to layout geometry and the resulting layout vs. loss tradeoffs are illustrated. A method of finding an optimal layout for a given converter application is developed and experimentally verified in a 50 MHz converter, resulting in a 35% reduction in power loss over an un-optimized device. It is further demonstrated that hot-carrier limits on device safe operating area may be relaxed under soft switching, yielding significant further loss reduction. A device fabricated with 20-V design rules is validated at 35-V, offering reduced parasitic resistance and capacitance. Compared to the original design, loss is up to 75% lower in the example application.
DepartmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science; Massachusetts Institute of Technology. Laboratory for Electromagnetic and Electronic Systems
IEEE Energy Conversion Congress and Exposition
Institute of Electrical and Electronics Engineers
Sagneri, A.D., D.I. Anderson, and D.J. Perreault. “Optimization of transistors for very high frequency dc-dc converters.” Energy Conversion Congress and Exposition, 2009. ECCE 2009. IEEE. 2009. 1590-1602. © 2009, IEEE
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INSPEC Accession Number: 10965461