A Micro-power EEG acquisition SoC with integrated seizure detection processor for continuous patient monitoring
Author(s)
Verma, Naveen; Shoeb, Ali H.; Chandrakasan, Anantha P.; Guttag, John V.
DownloadChandrakasan_A micro-power.pdf (1.259Mb)
PUBLISHER_POLICY
Publisher Policy
Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
Terms of use
Metadata
Show full item recordAbstract
Continuous on-scalp EEG monitoring provides a non-invasive means to detect the onset of seizures in epilepsy patients, but cables from the scalp pose a severe strangulation hazard during convulsions. Since the power of transmitting the EEG wirelessly is prohibitive, a complete SoC is presented, performing lowpower EEG acquisition, digitization, and local digital-processing to extract detection features, reducing the transmission-rate by 43x. To maximize power-efficiency, the acquisition LNA operates at the lowest reported VDD (of 1V, drawing 3.5muW), but is able to reject offsets (characteristic of metal-electrodes) that are even larger than the supply voltage. Importantly, its topology simultaneously optimizes noise-efficiency and input-impedance to maximize electrode signal-integrity, and it uses switch-capacitor transformers to improve the noise and manufactureabilty of large on-chip resistors. The complete SoC generates EEG featurevectors every 2sec, consuming a total of 9muJ per feature-vector.
Date issued
2009-08Department
Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory; Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science; Massachusetts Institute of Technology. Microsystems Technology LaboratoriesJournal
2009 Symposium on VLSI Circuits
Publisher
Institute of Electrical and Electronics Engineers
Citation
Verma, Naveen et al. “A Micro-power EEG acquisition SoC with integrated seizure detection processor for continuous patient monitoring.” VLSI Circuits, 2009 Symposium on. 2009. 62-63. ©2009 IEEE.
Version: Final published version
ISBN
978-1-4244-3307-0