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dc.contributor.authorDaniel, Luca
dc.contributor.authorEl-Moselhy, Tarek Ali
dc.date.accessioned2011-04-08T15:03:40Z
dc.date.available2011-04-08T15:03:40Z
dc.date.issued2010-04
dc.date.submitted2010-03
dc.identifier.isbn978-1-4244-7054-9
dc.identifier.issn1530-1591
dc.identifier.otherINSPEC Accession Number: 11283398
dc.identifier.urihttp://hdl.handle.net/1721.1/62170
dc.description.abstractIn this paper we present a stochastic model order reduction technique for interconnect extraction in the presence of process variabilities, i.e. variation-aware extraction. It is becoming increasingly evident that sampling based methods for variation-aware extraction are more efficient than more computationally complex techniques such as stochastic Galerkin method or the Neumann expansion. However, one of the remaining computational challenges of sampling based methods is how to simultaneously and efficiently solve the large number of linear systems corresponding to each different sample point. In this paper, we present a stochastic model reduction technique that exploits the similarity among the different solves to reduce the computational complexity of subsequent solves. We first suggest how to build a projection matrix such that the statistical moments and/or the coefficients of the projection of the stochastic vector on some orthogonal polynomials are preserved.We further introduce a proximity measure, which we use to determine apriori if a given system needs to be solved, or if it is instead properly represented using the currently available basis. Finally, in order to reduce the time required for the system assembly, we use the multivariate Hermite expansion to represent the system matrix. We verify our method by solving a variety of variation-aware capacitance extraction problems ranging from on-chip capacitance extraction in the presence of width and thickness variations, to off-chip capacitance extraction in the presence of surface roughness. We further solve very large scale problems that cannot be handled by any other state of the art technique.en_US
dc.description.sponsorshipSemiconductor Research Corporation. Focus Center Research Programen_US
dc.description.sponsorshipSemiconductor Research Corporation. Interconnect Focus Centeren_US
dc.language.isoen_US
dc.publisherInstitute of Electrical and Electronics Engineersen_US
dc.rightsArticle is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.en_US
dc.sourceIEEEen_US
dc.titleVariation-Aware Interconnect Extraction using Statistical Moment Preserving Model Order Reductionen_US
dc.typeArticleen_US
dc.identifier.citationEl-Moselhy, Tarek, and Luca Daniel. “Variation-aware Interconnect Extraction Using Statistical Moment Preserving Model Order Reduction.” Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010. 2010. 453-458. ©2010 IEEE.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Scienceen_US
dc.contributor.approverDaniel, Luca
dc.contributor.mitauthorDaniel, Luca
dc.contributor.mitauthorEl-Moselhy, Tarek Ali
dc.relation.journalDesign, Automation & Test in Europe Conference & Exhibition (DATE), 2010en_US
dc.eprint.versionFinal published versionen_US
dc.type.urihttp://purl.org/eprint/type/ConferencePaperen_US
dspace.orderedauthorsEl-Moselhy, Tarek; Daniel, Luca
dc.identifier.orcidhttps://orcid.org/0000-0002-5880-3151
mit.licensePUBLISHER_POLICYen_US
mit.metadata.statusComplete


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