A 512kb 8T SRAM macro operating down to 0.57V with an AC-coupled sense amplifier and embedded data-retention-voltage sensor in 45nm SOI CMOS
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An 8T SRAM fabricated in 45 nm SOI CMOS exhibits voltage scalable operation from 1.2 V down to 0.57 V with access times from 400 ps to 3.4 ns. Timing variation and the challenge of low-voltage operation are addressed with an AC-coupled sense amplifier. An area efficient data path is achieved with a regenerative global-bitline scheme. Finally, a data-retention-voltage sensor is developed to predict the mismatch-limited minimum-standby voltage without corrupting the content of the memory.
Date issued
2010-02Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science; Massachusetts Institute of Technology. Microsystems Technology LaboratoriesJournal
IEEE International Solid-State Circuits Conference (ISSCC). Digest of technical papers
Publisher
Institute of Electrical and Electronics Engineers
Citation
Qazi, M. et al. “A 512kb 8T SRAM Macro Operating down to 0.57V with an AC-coupled Sense Amplifier and Embedded Data-retention-voltage Sensor in 45nm SOI CMOS.” Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International. 2010. 350-351. Copyright © 2010, IEEE
Version: Final published version
Other identifiers
INSPEC Accession Number: 11204966
ISBN
978-1-4244-6033-5
ISSN
0193-6530