SWIFT: A SWing-reduced Interconnect For a Token-based Network-on-Chip in 90nm CMOS
Author(s)Krishna, Tushar; Postman, Jacob; Edmonds, Christopher; Peh, Li-Shiuan; Chang, Patrick
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With the advent of chip multi-processors (CMPs), on-chip networks are critical for providing low-power communications that scale to high core counts. With this motivation, we present a 64-bit, 8×8 mesh Network-on-Chip in 90nm CMOS that: (a) bypasses flit buffering in routers using Token Flow Control, thereby reducing buffer power along the control path, and (b) uses low-voltage-swing crossbars and links to reduce interconnect energy in the data path. These approaches enable 38% power savings and 39% latency reduction, when compared with an equivalent baseline network. An experimental 2×2 core prototype, operating at 400 MHz, validates our design.
DepartmentMassachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory; Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
IEEE International Conference on Computer Design (ICCD), 2010
Institute of Electrical and Electronics Engineers
Krishna, T. et al. “SWIFT: A SWing-reduced Interconnect for a Token-based Network-on-Chip in 90nm CMOS.” Computer Design (ICCD), 2010 IEEE International Conference On. 2010. 439-446. © 2010 IEEE.
Final published version
INSPEC Accession Number: 11675656