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SWIFT: A SWing-reduced Interconnect For a Token-based Network-on-Chip in 90nm CMOS

Author(s)
Krishna, Tushar; Postman, Jacob; Edmonds, Christopher; Peh, Li-Shiuan; Chang, Patrick
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Abstract
With the advent of chip multi-processors (CMPs), on-chip networks are critical for providing low-power communications that scale to high core counts. With this motivation, we present a 64-bit, 8×8 mesh Network-on-Chip in 90nm CMOS that: (a) bypasses flit buffering in routers using Token Flow Control, thereby reducing buffer power along the control path, and (b) uses low-voltage-swing crossbars and links to reduce interconnect energy in the data path. These approaches enable 38% power savings and 39% latency reduction, when compared with an equivalent baseline network. An experimental 2×2 core prototype, operating at 400 MHz, validates our design.
Date issued
2010-11
URI
http://hdl.handle.net/1721.1/63111
Department
Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory; Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Journal
IEEE International Conference on Computer Design (ICCD), 2010
Publisher
Institute of Electrical and Electronics Engineers
Citation
Krishna, T. et al. “SWIFT: A SWing-reduced Interconnect for a Token-based Network-on-Chip in 90nm CMOS.” Computer Design (ICCD), 2010 IEEE International Conference On. 2010. 439-446. © 2010 IEEE.
Version: Final published version
Other identifiers
INSPEC Accession Number: 11675656
ISBN
978-1-4244-8936-7
ISSN
1063-6404

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