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dc.contributor.authorKurian, George
dc.contributor.authorMiller, Jason E.
dc.contributor.authorPsota, James R.
dc.contributor.authorEastep, Jonathan Michael
dc.contributor.authorLiu, Jifeng
dc.contributor.authorMichel, Jurgen
dc.contributor.authorKimerling, Lionel C.
dc.contributor.authorAgarwal, Anant
dc.date.accessioned2011-12-09T18:32:35Z
dc.date.available2011-12-09T18:32:35Z
dc.date.issued2010-09
dc.identifier.isbn978-1-4503-0178-7
dc.identifier.urihttp://hdl.handle.net/1721.1/67490
dc.description.abstractBased on current trends, multicore processors will have 1000 cores or more within the next decade. However, their promise of increased performance will only be realized if their inherent scaling and programming challenges are overcome. Fortunately, recent advances in nanophotonic device manufacturing are making CMOS-integrated optics a reality-interconnect technology which can provide significantly more bandwidth at lower power than conventional electrical signaling. Optical interconnect has the potential to enable massive scaling and preserve familiar programming models in future multicore chips. This paper presents ATAC, a new multicore architecture with integrated optics, and ACKwise, a novel cache coherence protocol designed to leverage ATAC's strengths. ATAC uses nanophotonic technology to implement a fast, efficient global broadcast network which helps address a number of the challenges that future multicores will face. ACKwise is a new directory-based cache coherence protocol that uses this broadcast mechanism to provide high performance and scalability. Based on 64-core and 1024-core simulations with Splash2, Parsec, and synthetic benchmarks, we show that ATAC with ACKwise out-performs a chip with conventional interconnect and cache coherence protocols. On 1024-core evaluations, ACKwise protocol on ATAC outperforms the best conventional cache coherence protocol on an electrical mesh network by 2.5x with Splash2 benchmarks and by 61% with synthetic benchmarks.en_US
dc.description.sponsorshipNational Science Foundation (U.S.) (Grant No. 0811724)en_US
dc.language.isoen_US
dc.publisherAssociation for Computing Machineryen_US
dc.relation.isversionofhttp://dx.doi.org/10.1145/1854273.1854332en_US
dc.rightsCreative Commons Attribution-Noncommercial-Share Alike 3.0en_US
dc.rights.urihttp://creativecommons.org/licenses/by-nc-sa/3.0/en_US
dc.sourceMIT web domainen_US
dc.titleATAC: A 1000-Core Cache-Coherent Processor with On-Chip Optical Networken_US
dc.typeArticleen_US
dc.identifier.citationKurian, George et al. “ATAC.” ACM Press, 2010. 477. Web. 9 Dec. 2011. © 2010 Association for Computing Machineryen_US
dc.contributor.departmentMassachusetts Institute of Technology. Materials Processing Centeren_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Scienceen_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Materials Science and Engineeringen_US
dc.contributor.approverAgarwal, Anant
dc.contributor.mitauthorKurian, George
dc.contributor.mitauthorMiller, Jason E.
dc.contributor.mitauthorPsota, James R.
dc.contributor.mitauthorEastep, Jonathan Michael
dc.contributor.mitauthorLiu, Jifeng
dc.contributor.mitauthorMichel, Jurgen
dc.contributor.mitauthorKimerling, Lionel C.
dc.contributor.mitauthorAgarwal, Anant
dc.relation.journalProceedings of the 19th International Conference on Parallel Architectures and Compilation Techniquesen_US
dc.eprint.versionAuthor's final manuscripten_US
dc.type.urihttp://purl.org/eprint/type/ConferencePaperen_US
dspace.orderedauthorsKurian, George; Miller, Jason E.; Psota, James; Eastep, Jonathan; Liu, Jifeng; Michel, Jurgen; Kimerling, Lionel C.; Agarwal, Ananten
dc.identifier.orcidhttps://orcid.org/0000-0002-7015-4262
dc.identifier.orcidhttps://orcid.org/0000-0003-1371-7177
dc.identifier.orcidhttps://orcid.org/0000-0002-3913-6189
mit.licenseOPEN_ACCESS_POLICYen_US


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