ARCc: A case for an architecturally redundant cache-coherence architecture for large multicores
Author(s)Khan, Omer; Hoffmann, Henry Christian; Lis, Mieszko; Hijaz, Farrukh; Agarwal, Anant; Devadas, Srinivas; ... Show more Show less
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This paper proposes an architecturally redundant cache-coherence architecture (ARCc) that combines the directory and shared-NUCA based coherence protocols to improve performance, energy and dependability. Both coherence mechanisms co-exist in the hardware and ARCc enables seamless transition between the two protocols. We present an online analytical model implemented in the hardware that predicts performance and triggers a transition between the two coherence protocols at application-level granularity. The ARCc architecture delivers up to 1.6× higher performance and up to 1.5× lower energy consumption compared to the directory-based counterpart. It does so by identifying applications which benefit from the large shared cache capacity of shared-NUCA because of lower off-chip accesses, or where remote-cache word accesses are efficient.
DepartmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Proceedings of the IEEE International Conference on Computer Design, ICCD 2011
Institute of Electrical and Electronics Engineers
Khan, Omer et al. “ARCc: A Case for an Architecturally Redundant Cache-coherence Architecture for Large Multicores.” IEEE, 2011. 411–418. Web.
Author's final manuscript
INSPEC Accession Number: 12386634