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dc.contributor.authorTsuk, Michael
dc.contributor.authorDvorscak, Daniel
dc.contributor.authorOng, Chin Siong
dc.contributor.authorWhite, Jacob K.
dc.date.accessioned2012-07-27T18:31:13Z
dc.date.available2012-07-27T18:31:13Z
dc.date.issued2009-12
dc.date.submitted2009-11
dc.identifier.isbn978-1-60558-800-1
dc.identifier.isbn978-1-60558-800-1
dc.identifier.issn1092-3152
dc.identifier.urihttp://hdl.handle.net/1721.1/71877
dc.description.abstractrute-force simulation approaches to estimating serial-link bit-error rates (BERs) become computationally intractable for the case when BERs are low and the interconnect electrical response is slow enough to generate intersymbol interference that spans dozens of bit periods. Electrical-level statistical simulation approaches based on superposing pulse responses were developed to address this problem, but such pulse-based methods have difficulty analyzing jitter and rise/fall asymmetry. In this paper we present a superposing-edge approach for statistical simulation, as edge-based methods handle rise/fall asymmetry and jitter in straightforward way. We also resolve a key problem in using edge-based approaches, that edges are always correlated, by deriving an efficient inductive approach for propagating the edge correlations. Examples are presented demonstrating the edge-based method's accuracy and effectiveness in analyzing combinations of uniform, Gaussian, and periodic distributed random jitter.en_US
dc.language.isoen_US
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en_US
dc.relation.isversionofhttp://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5361218en_US
dc.rightsArticle is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.en_US
dc.sourceIEEEen_US
dc.titleAn electrical-level superposed-edge approach to statistical serial link simulationen_US
dc.typeArticleen_US
dc.identifier.citationTsuk, M. et al. "An electrical-level superposed-edge approach to statistical serial link simulation." IEEE, 2009. 717-724. © Copyright 2009 IEEEen_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Scienceen_US
dc.contributor.approverWhite, Jacob K.
dc.contributor.mitauthorWhite, Jacob K.
dc.relation.journalIEEE/ACM International Conference on Computer-Aided Design Digest of Technical Papers, 2009en_US
dc.eprint.versionFinal published versionen_US
dc.type.urihttp://purl.org/eprint/type/ConferencePaperen_US
dspace.orderedauthorsTusk, Michael; Dvorscak, Daniel; Chin Siong Ong; White, Jacoben_US
dc.identifier.orcidhttps://orcid.org/0000-0003-1080-4005
mit.licensePUBLISHER_POLICYen_US
mit.metadata.statusComplete


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