A CMOS Imager With a Programmable Bit-Serial Column-Parallel SIMD/MIMD Processor

Abstract

An imager with an integrated fully programmable bit-serial column-parallel processor is proposed to meet the demand for a compact and versatile system-on-imager chip for consumer applications. The on-imager processor is targeting a computationally intensive low-level image processing task. The processor is physically arranged as a densely packed 2-D processing element (PE) array at an imager column level. The digital processor has a multiple-instruction-multiple-data (MIMD) architecture configuring multiple column-parallel single-instruction-multiple-data (SIMD) processors. The prototype imager chip with 128 times 128 pixels and 4 times 128 PE array designed with 0.6-mum technology was fabricated, and its functionality was tested. The estimation of performance level of the proposed processor architecture with an advanced technology such as the 0.09-mum process technology shows that the proposed imager chip architecture has a potential of giga sum operations per second per square millimeter class processing performance.