Zero-crossing detector based reconfigurable analog system

Author(s)
Lajevardi, Payam; Chandrakasan, Anantha P.; Lee, Hae-Seung
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Abstract
A reconfigurable analog system is presented that implements pipelined ADCs, switched-capacitor filters, and programmable gain amplifiers. Each block employs a zero-crossing based circuit for easy reconfigurability and power efficiency. Configured as a 10-bit ADC, the chip consumes 1.92mW at 50MSPS with ENOB of 8.02b and FOM of 150fJ/conversion-step. A third order Butterworth filter is also demonstrated. The chip is implemented in 65nm technology.
Date issued
2010-11
URI
http://hdl.handle.net/1721.1/72194
Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Journal
2010 IEEE Asian Solid State Circuits Conference (A-SSCC)
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Lajevardi, P, A Chandrakasan, and Hae-Seung Lee. “Zero-crossing Detector Based Reconfigurable Analog System.” 2010 IEEE Asian Solid State Circuits Conference (A-SSCC), 2010. 1–4. © Copyright 2010 IEEE
Version: Final published version
ISSN
978-1-4244-8300-6
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