dc.contributor.author | Lis, Mieszko | |
dc.contributor.author | Shim, Keun Sup | |
dc.contributor.author | Cho, Myong Hyon | |
dc.contributor.author | Fletcher, Christopher Wardlaw | |
dc.contributor.author | Kinsy, Michel A. | |
dc.contributor.author | Lebedev, Ilia A. | |
dc.contributor.author | Khan, Omer | |
dc.contributor.author | Devadas, Srinivas | |
dc.date.accessioned | 2012-08-27T20:39:51Z | |
dc.date.available | 2012-08-27T20:39:51Z | |
dc.date.issued | 2011-06 | |
dc.identifier.isbn | 978-1-4503-0743-7 | |
dc.identifier.uri | http://hdl.handle.net/1721.1/72358 | |
dc.description.abstract | Driven by increasingly unbalanced technology scaling and power
dissipation limits, microprocessor designers have resorted to increasing
the number of cores on a single chip, and pundits expect
1000-core designs to materialize in the next few years [1]. But how
will memory architectures scale and how will these next-generation
multicores be programmed?
One barrier to scaling current memory architectures is the offchip
memory bandwidth wall [1,2]: off-chip bandwidth grows with
package pin density, which scales much more slowly than on-die
transistor density [3]. To reduce reliance on external memories and
keep data on-chip, today’s multicores integrate very large shared
last-level caches on chip [4]; interconnects used with such shared
caches, however, do not scale beyond relatively few cores, and the
power requirements and access latencies of large caches exclude
their use in chips on a 1000-core scale. For massive-scale multicores,
then, we are left with relatively small per-core caches.
Per-core caches on a 1000-core scale, in turn, raise the question
of memory coherence. On the one hand, a shared memory abstraction
is a practical necessity for general-purpose programming, and
most programmers prefer a shared memory model [5]. On the other
hand, ensuring coherence among private caches is an expensive
proposition: bus-based and snoopy protocols don’t scale beyond
relatively few cores, and directory sizes needed in cache-coherence
protocols must equal a significant portion of the combined size of
the per-core caches as otherwise directory evictions will limit performance
[6]. Moreover, directory-based coherence protocols are
notoriously difficult to implement and verify [7]. | en_US |
dc.language.iso | en_US | |
dc.publisher | Association for Computing Machinery (ACM) | en_US |
dc.relation.isversionof | http://dx.doi.org/10.1145/1989493.1989530 | en_US |
dc.rights | Creative Commons Attribution-Noncommercial-Share Alike 3.0 | en_US |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-sa/3.0/ | en_US |
dc.source | MIT web domain | en_US |
dc.title | Brief announcement: Distributed shared memory based on computation migration | en_US |
dc.type | Article | en_US |
dc.identifier.citation | Mieszko Lis, Keun Sup Shim, Myong Hyon Cho, Christopher W. Fletcher, Michel Kinsy, Ilia Lebedev, Omer Khan, and Srinivas Devadas. 2011. Brief announcement: distributed shared memory based on computation migration. In Proceedings of the 23rd ACM symposium on Parallelism in algorithms and architectures (SPAA '11). ACM, New York, NY, USA, 253-256. | en_US |
dc.contributor.department | Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory | en_US |
dc.contributor.department | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science | en_US |
dc.contributor.approver | Devadas, Srinivas | |
dc.contributor.mitauthor | Lis, Mieszko | |
dc.contributor.mitauthor | Shim, Keun Sup | |
dc.contributor.mitauthor | Cho, Myong Hyon | |
dc.contributor.mitauthor | Fletcher, Christopher Wardlaw | |
dc.contributor.mitauthor | Kinsy, Michel A. | |
dc.contributor.mitauthor | Lebedev, Ilia A. | |
dc.contributor.mitauthor | Khan, Omer | |
dc.contributor.mitauthor | Devadas, Srinivas | |
dc.relation.journal | Proceedings of the 23rd ACM Symposium on Parallelism in Algorithms and Architectures (SPAA '11) | en_US |
dc.eprint.version | Author's final manuscript | en_US |
dc.type.uri | http://purl.org/eprint/type/ConferencePaper | en_US |
dspace.orderedauthors | Lis, Mieszko; Shim, Keun Sup; Cho, Myong Hyon; Fletcher, Christopher W.; Kinsy, Michel; Lebedev, Ilia; Khan, Omer; Devadas, Srinivas | en |
dc.identifier.orcid | https://orcid.org/0000-0001-8253-7714 | |
dc.identifier.orcid | https://orcid.org/0000-0003-4301-1159 | |
dc.identifier.orcid | https://orcid.org/0000-0001-5490-2323 | |
dc.identifier.orcid | https://orcid.org/0000-0003-1467-2150 | |
dspace.mitauthor.error | true | |
mit.license | OPEN_ACCESS_POLICY | en_US |
mit.metadata.status | Complete | |