Thermal considerations for advanced SOI substrates designed for III-V/Si heterointegration

Abstract

Silicon-on-lattice engineered substrates (SOLES) are SOI substrates with embedded Ge layers that facilitate III-V compound integration for advanced integrated circuits. The new materials integration scheme in SOLES requires the analysis of its thermal stability and diffusion barrier properties. In this study, we report on the successful monolithic integration of CMOS/III-V transistors with a reduced CMOS thermal budget. We further investigated the ultimate thermal budget limits for the SOLES platform. We demonstrated a new SOLES structure incorporating a SiNx interlayer, which adds greater integration flexibility for future circuit applications.