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dc.contributor.authorRapoport, Benjamin I.
dc.contributor.authorTuricchia, Lorenzo
dc.contributor.authorWattanapanitch, Woradorn
dc.contributor.authorDavidson, Thomas J.
dc.contributor.authorSarpeshkar, Rahul
dc.date.accessioned2012-11-14T15:07:17Z
dc.date.available2012-11-14T15:07:17Z
dc.date.issued2012-09
dc.date.submitted2011-06
dc.identifier.issn1932-6203
dc.identifier.urihttp://hdl.handle.net/1721.1/74634
dc.description.abstractThe ability to decode neural activity into meaningful control signals for prosthetic devices is critical to the development of clinically useful brain– machine interfaces (BMIs). Such systems require input from tens to hundreds of brain-implanted recording electrodes in order to deliver robust and accurate performance; in serving that primary function they should also minimize power dissipation in order to avoid damaging neural tissue; and they should transmit data wirelessly in order to minimize the risk of infection associated with chronic, transcutaneous implants. Electronic architectures for brain– machine interfaces must therefore minimize size and power consumption, while maximizing the ability to compress data to be transmitted over limited-bandwidth wireless channels. Here we present a system of extremely low computational complexity, designed for real-time decoding of neural signals, and suited for highly scalable implantable systems. Our programmable architecture is an explicit implementation of a universal computing machine emulating the dynamics of a network of integrate-and-fire neurons; it requires no arithmetic operations except for counting, and decodes neural signals using only computationally inexpensive logic operations. The simplicity of this architecture does not compromise its ability to compress raw neural data by factors greater than . We describe a set of decoding algorithms based on this computational architecture, one designed to operate within an implanted system, minimizing its power consumption and data transmission bandwidth; and a complementary set of algorithms for learning, programming the decoder, and postprocessing the decoded output, designed to operate in an external, nonimplanted unit. The implementation of the implantable portion is estimated to require fewer than 5000 operations per second. A proof-of-concept, 32-channel field-programmable gate array (FPGA) implementation of this portion is consequently energy efficient. We validate the performance of our overall system by decoding electrophysiologic data from a behaving rodent.en_US
dc.description.sponsorshipUnited States. National Institutes of Health (Grant NS056140)en_US
dc.language.isoen_US
dc.publisherPublic Library of Scienceen_US
dc.relation.isversionofhttp://dx.doi.org/10.1371/journal.pone.0042492en_US
dc.rightsCreative Commons Attributionen_US
dc.rights.urihttp://creativecommons.org/licenses/by/2.5/en_US
dc.sourcePLoSen_US
dc.titleEfficient Universal Computing Architectures for Decoding Neural Activityen_US
dc.typeArticleen_US
dc.identifier.citationRapoport, Benjamin I. et al. “Efficient Universal Computing Architectures for Decoding Neural Activity.” Ed. Michal Zochowski. PLoS ONE 7.9 (2012).en_US
dc.contributor.departmentHarvard University--MIT Division of Health Sciences and Technologyen_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Scienceen_US
dc.contributor.mitauthorRapoport, Benjamin I.
dc.contributor.mitauthorTuricchia, Lorenzo
dc.contributor.mitauthorSarpeshkar, Rahul
dc.relation.journalPLoS ONEen_US
dc.eprint.versionFinal published versionen_US
dc.type.urihttp://purl.org/eprint/type/JournalArticleen_US
eprint.statushttp://purl.org/eprint/status/PeerRevieweden_US
dspace.orderedauthorsRapoport, Benjamin I.; Turicchia, Lorenzo; Wattanapanitch, Woradorn; Davidson, Thomas J.; Sarpeshkar, Rahulen
dc.identifier.orcidhttps://orcid.org/0000-0003-0384-3786
mit.licensePUBLISHER_CCen_US
mit.metadata.statusComplete


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