| dc.contributor.author | Eusner, Thor | |
| dc.contributor.author | Saka, Nannaji | |
| dc.contributor.author | Chun, Jung-Hoon | |
| dc.date.accessioned | 2013-04-10T19:52:25Z | |
| dc.date.available | 2013-04-10T19:52:25Z | |
| dc.date.issued | 2010-10 | |
| dc.identifier.isbn | 978-4-9904138-3-5 | |
| dc.identifier.isbn | 978-1-4577-0392-8 | |
| dc.identifier.issn | 1523-553X | |
| dc.identifier.other | ISSM 2010 POO-032 | |
| dc.identifier.other | INSPEC Accession Number: 11945567 | |
| dc.identifier.uri | http://hdl.handle.net/1721.1/78335 | |
| dc.description.abstract | The chemical-mechanical polishing (CMP) of Cu is a critical step in the manufacture of ultra-large-scale integrated (ULSl) semiconductor devices. During this process, undesirable scratches are formed on the surface being polished [I -3]. Recent research suggests that the "killer" scratches found on the Cu wafers are due to the soft pad asperities and not necessarily by the hard abrasives in the slurry [4,5]. Figure 1 shows examples of scratches on a Cu coating due to pad asperities. This paper presents the theory and experimental validation of scratching by soft pad asperities in Cu CMP. Based on the models and experimental results, practical solutions for mitigating scratching by pad asperities in Cu CMP are suggested. | en_US |
| dc.language.iso | en_US | |
| dc.publisher | Institute of Electrical and Electronics Engineers | en_US |
| dc.relation.isversionof | http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5750240 | en_US |
| dc.rights | Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use. | en_US |
| dc.source | IEEE | en_US |
| dc.title | Defect reduction in Cu chemical-mechanical polishing | en_US |
| dc.type | Article | en_US |
| dc.identifier.citation | Eusner, Thor, Nannaji Saka,and Jung-Hoon Chun. "Defect Reduction in Cu Chemical-Mechanical Polishing." ISSM 2010 conference proceedings, the Eighteenth International Symposium on Semiconductor Manufacturing, October 18-20, 2010, Hyatt Regency Tokyo, Shinjuku, Tokyo. IEEE, 2010. © Copyright 2010 IEEE. | en_US |
| dc.contributor.department | Massachusetts Institute of Technology. Laboratory for Manufacturing and Productivity | en_US |
| dc.contributor.mitauthor | Eusner, Thor | |
| dc.contributor.mitauthor | Saka, Nannaji | |
| dc.contributor.mitauthor | Chun, Jung-Hoon | |
| dc.relation.journal | Proceedings of the Eighteenth International Symposium on Semiconductor Manufacturing, ISSM 2010 | en_US |
| dc.eprint.version | Final published version | en_US |
| dc.type.uri | http://purl.org/eprint/type/ConferencePaper | en_US |
| dspace.orderedauthors | Eusner, Thor; Saka, Nannaji; Chun, Jung-Hoon | en_US |
| dc.identifier.orcid | https://orcid.org/0000-0002-8480-5572 | |
| dc.identifier.orcid | https://orcid.org/0000-0003-1607-3581 | |
| mit.license | PUBLISHER_POLICY | en_US |
| mit.metadata.status | Complete | |