Simulated Co-Optimization of Crystalline Silicon Solar Cell Throughput and Efficiency Using Continuously Ramping Phosphorus Diffusion Profiles

Abstract

Defect engineering is essential for the production of high-performance silicon photovoltaic (PV) devices with cost-effective solar-grade Si input materials. Phosphorus diffusion gettering (PDG) can mitigate the detrimental effect of metal impurities on PV device performance. Using the Impurity-to-Efficiency (I2E) simulator, we investigate the effect of gettering temperature on minority carrier lifetime while maintaining an approximately constant sheet resistance. We simulate a typical constant temperature plateau profile and an alternative “volcano” profile that consists of a ramp up to a peak temperature above the typical plateau temperature followed by a ramp down with no hold time. Our simulations show that for a given PDG process time, the “volcano” produces an increase in minority carrier lifetime compared to the standard plateau profile for as-grown iron distributions that are typical for multicrystalline silicon. For an initial total iron concentration of 5×1013 cm-3, we simulate a 30% increase in minority carrier lifetime for a fixed PDG process time and a 43% reduction in PDG process cost for a given effective minority carrier lifetime while achieving a constant sheet resistance of 100 Ω/□.