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dc.contributor.authorPerry, Jonathan
dc.contributor.authorIannucci, Peter A.
dc.contributor.authorFleming, Kermin Elliott
dc.contributor.authorBalakrishnan, Hari
dc.contributor.authorShah, Devavrat
dc.date.accessioned2014-03-27T20:42:38Z
dc.date.available2014-03-27T20:42:38Z
dc.date.issued2012-10
dc.date.submitted2012-08
dc.identifier.issn01464833
dc.identifier.issn1943-5819
dc.identifier.urihttp://hdl.handle.net/1721.1/85938
dc.description.abstractSpinal codes are a new class of rateless codes that enable wireless networks to cope with time-varying channel conditions in a natural way, without requiring any explicit bit rate selection. The key idea in the code is the sequential application of a pseudo-random hash function to the message bits to produce a sequence of coded symbols for transmission. This encoding ensures that two input messages that differ in even one bit lead to very different coded sequences after the point at which they differ, providing good resilience to noise and bit errors. To decode spinal codes, this paper develops an approximate maximum-likelihood decoder, called the bubble decoder, which runs in time polynomial in the message size and achieves the Shannon capacity over both additive white Gaussian noise (AWGN) and binary symmetric channel (BSC) models. Experimental results obtained from a software implementation of a linear-time decoder show that spinal codes achieve higher throughput than fixed-rate LDPC codes, rateless Raptor codes, and the layered rateless coding approach of Strider, across a range of channel conditions and message sizes. An early hardware prototype that can decode at 10 Mbits/s in FPGA demonstrates that spinal codes are a practical construction.en_US
dc.description.sponsorshipMassachusetts Institute of Technology (Irwin and Joan Jacobs Presidential Fellowship)en_US
dc.description.sponsorshipMassachusetts Institute of Technology (Claude E. Shannon Assistantship)en_US
dc.description.sponsorshipIntel Corporation (Intel Fellowship)en_US
dc.language.isoen_US
dc.publisherAssociation for Computing Machineryen_US
dc.relation.isversionofhttp://dx.doi.org/10.1145/2377677.2377684en_US
dc.rightsCreative Commons Attribution-Noncommercial-Share Alikeen_US
dc.rights.urihttp://creativecommons.org/licenses/by-nc-sa/4.0/en_US
dc.sourceMIT web domainen_US
dc.titleSpinal codesen_US
dc.typeArticleen_US
dc.identifier.citationPerry, Jonathan, Peter A. Iannucci, Kermin E. Fleming, Hari Balakrishnan, and Devavrat Shah. “Spinal Codes.” ACM SIGCOMM Computer Communication Review 42, no. 4 (October 2012): 49-60.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Scienceen_US
dc.contributor.mitauthorPerry, Jonathanen_US
dc.contributor.mitauthorIannucci, Peter A.en_US
dc.contributor.mitauthorFleming, Kermin Elliotten_US
dc.contributor.mitauthorBalakrishnan, Harien_US
dc.contributor.mitauthorShah, Devavraten_US
dc.relation.journalACM SIGCOMM Computer Communication Reviewen_US
dc.eprint.versionAuthor's final manuscripten_US
dc.type.urihttp://purl.org/eprint/type/ConferencePaperen_US
eprint.statushttp://purl.org/eprint/status/NonPeerRevieweden_US
dspace.orderedauthorsPerry, Jonathan; Iannucci, Peter A.; Fleming, Kermin E.; Balakrishnan, Hari; Shah, Devavraten_US
dc.identifier.orcidhttps://orcid.org/0000-0002-6465-7023
dc.identifier.orcidhttps://orcid.org/0000-0002-4566-771X
dc.identifier.orcidhttps://orcid.org/0000-0003-0737-3259
dc.identifier.orcidhttps://orcid.org/0000-0002-1455-9652
mit.licenseOPEN_ACCESS_POLICYen_US
mit.metadata.statusComplete


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