| dc.contributor.author | Pilawa-Podgurski, Robert C. N. | |
| dc.contributor.author | Perreault, David J. | |
| dc.date.accessioned | 2014-05-22T17:21:20Z | |
| dc.date.available | 2014-05-22T17:21:20Z | |
| dc.date.issued | 2012-05 | |
| dc.date.submitted | 2012-02 | |
| dc.identifier.issn | 0018-9200 | |
| dc.identifier.issn | 1558-173X | |
| dc.identifier.uri | http://hdl.handle.net/1721.1/87099 | |
| dc.description.abstract | In this paper, we introduce a merged two-stage dc-dc power converter for low-voltage power delivery. By separating the transformation and regulation function of a dc-dc power converter into two stages, both large voltage transformation and high switching frequency can be achieved. We show how the switched-capacitor stage can operate under soft charging conditions by suitable control and integration (merging) of the two stages. This mode of operation enables improved efficiency and/or power density in the switched-capacitor stage. A 5-to-1 V, 0.8 W integrated dc-dc converter has been developed in 180 nm CMOS. The converter achieves a peak efficiency of 81%, with a regulation stage switching frequency of 10 MHz. | en_US |
| dc.description.sponsorship | Interconnect Focus Center (United States. Defense Advanced Research Projects Agency and Semiconductor Research Corporation) | en_US |
| dc.language.iso | en_US | |
| dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en_US |
| dc.relation.isversionof | http://dx.doi.org/10.1109/JSSC.2012.2191325 | en_US |
| dc.rights | Creative Commons Attribution-Noncommercial-Share Alike | en_US |
| dc.rights.uri | http://creativecommons.org/licenses/by-nc-sa/4.0/ | en_US |
| dc.source | Vabulas | en_US |
| dc.title | Merged Two-Stage Power Converter With Soft Charging Switched-Capacitor Stage in 180 nm CMOS | en_US |
| dc.type | Article | en_US |
| dc.identifier.citation | Pilawa-Podgurski, Robert C. N., and David J. Perreault. “Merged Two-Stage Power Converter With Soft Charging Switched-Capacitor Stage in 180 Nm CMOS.” IEEE Journal of Solid-State Circuits 47, no. 7 (n.d.): 1557–1567. | en_US |
| dc.contributor.department | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science | en_US |
| dc.contributor.approver | Perreault, David J. | en_US |
| dc.contributor.mitauthor | Pilawa-Podgurski, Robert C. N. | en_US |
| dc.contributor.mitauthor | Perreault, David J. | en_US |
| dc.relation.journal | IEEE Journal of Solid-State Circuits | en_US |
| dc.eprint.version | Author's final manuscript | en_US |
| dc.type.uri | http://purl.org/eprint/type/JournalArticle | en_US |
| eprint.status | http://purl.org/eprint/status/PeerReviewed | en_US |
| dspace.orderedauthors | Pilawa-Podgurski, Robert C. N.; Perreault, David J. | en_US |
| dc.identifier.orcid | https://orcid.org/0000-0002-0746-6191 | |
| mit.license | OPEN_ACCESS_POLICY | en_US |
| mit.metadata.status | Complete | |
