| dc.contributor.author | Lee, I-Ting Angelina | |
| dc.contributor.author | Shafi, Aamir | |
| dc.contributor.author | Leiserson, Charles E. | |
| dc.date.accessioned | 2014-09-22T16:56:23Z | |
| dc.date.available | 2014-09-22T16:56:23Z | |
| dc.date.issued | 2012-06 | |
| dc.identifier.isbn | 9781450312134 | |
| dc.identifier.uri | http://hdl.handle.net/1721.1/90259 | |
| dc.description.abstract | Reducer hyperobjects (reducers) provide a linguistic abstraction for dynamic multithreading that allows different branches of a parallel program to maintain coordinated local views of the same nonlocal variable. In this paper, we investigate how thread-local memory mapping (TLMM) can be used to improve the performance of reducers. Existing concurrency platforms that support reducer hyperobjects, such as Intel Cilk Plus and Cilk++, take a hypermap approach in which a hash table is used to map reducer objects to their local views. The overhead of the hash table is costly --- roughly 12x overhead compared to a normal L1-cache memory access on an AMD Opteron 8354. We replaced the Intel Cilk Plus runtime system with our own Cilk-M runtime system which uses TLMM to implement a reducer mechanism that supports a reducer lookup using only two memory accesses and a predictable branch, which is roughly a 3x overhead compared to an ordinary L1-cache memory access. An empirical evaluation shows that the Cilk-M memory-mapping approach is close to 4x faster than the Cilk Plus hypermap approach. Furthermore, the memory-mapping approach admits better locality than the hypermap approach during parallel execution, which allows an application using reducers to scale better. | en_US |
| dc.description.sponsorship | National Science Foundation (U.S.) (Grant CNS-1017058) | en_US |
| dc.language.iso | en_US | |
| dc.publisher | Association for Computing Machinery (ACM) | en_US |
| dc.relation.isversionof | http://dx.doi.org/10.1145/2312005.2312056 | en_US |
| dc.rights | Creative Commons Attribution-Noncommercial-Share Alike | en_US |
| dc.rights.uri | http://creativecommons.org/licenses/by-nc-sa/4.0/ | en_US |
| dc.source | MIT web domain | en_US |
| dc.title | Memory-mapping support for reducer hyperobjects | en_US |
| dc.type | Article | en_US |
| dc.identifier.citation | I-Ting Angelina Lee, Aamir Shafi, and Charles E. Leiserson. 2012. Memory-mapping support for reducer hyperobjects. In Proceedings of the twenty-fourth annual ACM symposium on Parallelism in algorithms and architectures (SPAA '12). ACM, New York, NY, USA, 287-297. | en_US |
| dc.contributor.department | Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory | en_US |
| dc.contributor.department | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science | en_US |
| dc.contributor.mitauthor | Lee, I-Ting Angelina | en_US |
| dc.contributor.mitauthor | Leiserson, Charles E. | en_US |
| dc.relation.journal | Proceedinbgs of the 24th ACM symposium on Parallelism in algorithms and architectures (SPAA '12) | en_US |
| dc.eprint.version | Author's final manuscript | en_US |
| dc.type.uri | http://purl.org/eprint/type/JournalArticle | en_US |
| eprint.status | http://purl.org/eprint/status/PeerReviewed | en_US |
| dspace.orderedauthors | Lee, I-Ting Angelina; Shafi, Aamir; Leiserson, Charles E. | en_US |
| mit.license | OPEN_ACCESS_POLICY | en_US |
| mit.metadata.status | Complete | |