Jigsaw: Scalable software-defined caches
Author(s)Beckmann, Nathan Zachary; Sanchez, Daniel
MetadataShow full item record
Shared last-level caches, widely used in chip-multi-processors (CMPs), face two fundamental limitations. First, the latency and energy of shared caches degrade as the system scales up. Second, when multiple workloads share the CMP, they suffer from interference in shared cache accesses. Unfortunately, prior research addressing one issue either ignores or worsens the other: NUCA techniques reduce access latency but are prone to hotspots and interference, and cache partitioning techniques only provide isolation but do not reduce access latency.
DepartmentMassachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory; Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Proceedings of the 2013 22nd International Conference on Parallel Architectures and Compilation Techniques (PACT)
Institute of Electrical and Electronics Engineers (IEEE)
Beckmann, Nathan and Daniel Sanchez. "Jigsaw: Scalable software-defined caches." In 2013 22nd International Conference on Parallel Architectures and Compilation Techniques, 7-11 Sept. 2013, Edinburgh, Scotland. IEEE, p.213-224.
Author's final manuscript
INSPEC Accession Number: 13826450