| dc.contributor.author | Paidimarri, Arun | |
| dc.contributor.author | Mercier, Patrick Philip | |
| dc.contributor.author | Chandrakasan, Anantha P. | |
| dc.contributor.author | Nadeau, Phillip | |
| dc.date.accessioned | 2015-01-13T19:00:24Z | |
| dc.date.available | 2015-01-13T19:00:24Z | |
| dc.date.issued | 2012-06 | |
| dc.identifier.isbn | 978-1-4673-0849-6 | |
| dc.identifier.isbn | 978-1-4673-0848-9 | |
| dc.identifier.isbn | 978-1-4673-0845-8 | |
| dc.identifier.uri | http://hdl.handle.net/1721.1/92831 | |
| dc.description.abstract | A 2.4GHz TX in 65nm CMOS defines three channels using three high-Q FBARs and supports OOK, BPSK and MSK. The oscillators have -132dBc/Hz phase noise at 1MHz offset, and are multiplexed to an efficient resonant buffer. Optimized for low output power ≈-10dBm, a fully-integrated PA implements 7.5dB dynamic output power range using a dynamic impedance transformation network, and is used for amplitude pulse-shaping. Peak PA efficiency is 44.4% and peak TX efficiency is 33%. The entire TX consumes 440pJ/bit at 1Mb/s. | en_US |
| dc.description.sponsorship | Interconnect Focus Center (United States. Defense Advanced Research Projects Agency and Semiconductor Research Corporation) | en_US |
| dc.language.iso | en_US | |
| dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en_US |
| dc.relation.isversionof | http://dx.doi.org/10.1109/VLSIC.2012.6243776 | en_US |
| dc.rights | Creative Commons Attribution-Noncommercial-Share Alike | en_US |
| dc.rights.uri | http://creativecommons.org/licenses/by-nc-sa/4.0/ | en_US |
| dc.source | Paidimarri | en_US |
| dc.title | A 440pJ/bit 1Mb/s 2.4GHz multi-channel FBAR-based TX and an integrated pulse-shaping PA | en_US |
| dc.type | Article | en_US |
| dc.identifier.citation | Paidimarri, Arun, Phillip M. Nadeau, Patrick P. Mercier, and Anantha P. Chandrakasan. “A 440pJ/bit 1Mb/s 2.4GHz Multi-Channel FBAR-Based TX and an Integrated Pulse-Shaping PA.” 2012 Symposium on VLSI Circuits (VLSIC) (June 2012). | en_US |
| dc.contributor.department | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science | en_US |
| dc.contributor.approver | Chandrakasan, Anantha P. | en_US |
| dc.contributor.mitauthor | Paidimarri, Arun | en_US |
| dc.contributor.mitauthor | Nadeau, Phillip | en_US |
| dc.contributor.mitauthor | Mercier, Patrick Philip | en_US |
| dc.contributor.mitauthor | Chandrakasan, Anantha P. | en_US |
| dc.relation.journal | Proceedings of the 2012 Symposium on VLSI Circuits (VLSIC) | en_US |
| dc.eprint.version | Author's final manuscript | en_US |
| dc.type.uri | http://purl.org/eprint/type/ConferencePaper | en_US |
| eprint.status | http://purl.org/eprint/status/NonPeerReviewed | en_US |
| dspace.orderedauthors | Paidimarri, Arun; Nadeau, Phillip M.; Mercier, Patrick P.; Chandrakasan, Anantha P. | en_US |
| dc.identifier.orcid | https://orcid.org/0000-0002-7820-1625 | |
| dc.identifier.orcid | https://orcid.org/0000-0003-0493-337X | |
| dc.identifier.orcid | https://orcid.org/0000-0002-5977-2748 | |
| dspace.mitauthor.error | true | |
| mit.license | OPEN_ACCESS_POLICY | en_US |
| mit.metadata.status | Complete | |
