| dc.contributor.author | Paidimarri, Arun | |
| dc.contributor.author | Mercier, Patrick Philip | |
| dc.contributor.author | Chandrakasan, Anantha P. | |
| dc.contributor.author | Nadeau, Phillip | |
| dc.date.accessioned | 2015-01-21T16:57:10Z | |
| dc.date.available | 2015-01-21T16:57:10Z | |
| dc.date.issued | 2013-01 | |
| dc.date.submitted | 2012-11 | |
| dc.identifier.issn | 0018-9200 | |
| dc.identifier.issn | 1558-173X | |
| dc.identifier.uri | http://hdl.handle.net/1721.1/93089 | |
| dc.description.abstract | A 2.4 GHz TX in 65 nm CMOS defines three channels using three high-Q FBARs and supports OOK, BPSK and MSK. The oscillators have -132 [dBc over Hz] phase noise at 1 MHz offset, and are multiplexed to an efficient resonant buffer. Optimized for low output power ≈ -10 dBm, a fully-integrated PA implements 7.5 dB dynamic output power range using a dynamic impedance transformation network, and is used for amplitude pulse-shaping. Peak PA efficiency is 44.4% and peak TX efficiency is 33%. The entire TX consumes 440 [pJ over bit] at 1 [Mb over s]. | en_US |
| dc.description.sponsorship | Focus Center Research Program. Focus Center for Circuit & System Solutions. Semiconductor Research Corporation. Interconnect Focus Center | en_US |
| dc.language.iso | en_US | |
| dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en_US |
| dc.relation.isversionof | http://dx.doi.org/10.1109/JSSC.2013.2239001 | en_US |
| dc.rights | Creative Commons Attribution-Noncommercial-Share Alike | en_US |
| dc.rights.uri | http://creativecommons.org/licenses/by-nc-sa/4.0/ | en_US |
| dc.source | Arun Paidimarri | en_US |
| dc.title | A 2.4 GHz Multi-Channel FBAR-based Transmitter With an Integrated Pulse-Shaping Power Amplifier | en_US |
| dc.type | Article | en_US |
| dc.identifier.citation | Paidimarri, Arun, Phillip M. Nadeau, Patrick P. Mercier, and Anantha P. Chandrakasan. “A 2.4 GHz Multi-Channel FBAR-Based Transmitter With an Integrated Pulse-Shaping Power Amplifier.” IEEE Journal of Solid-State Circuits 48, no. 4 (April 2013): 1042–1054. | en_US |
| dc.contributor.department | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science | en_US |
| dc.contributor.approver | Chandrakasan, Anantha P. | en_US |
| dc.contributor.mitauthor | Chandrakasan, Anantha P. | en_US |
| dc.contributor.mitauthor | Paidimarri, Arun | en_US |
| dc.contributor.mitauthor | Nadeau, Phillip | en_US |
| dc.relation.journal | IEEE Journal of Solid-State Circuits | en_US |
| dc.eprint.version | Author's final manuscript | en_US |
| dc.type.uri | http://purl.org/eprint/type/JournalArticle | en_US |
| eprint.status | http://purl.org/eprint/status/PeerReviewed | en_US |
| dspace.orderedauthors | Paidimarri, Arun; Nadeau, Phillip M.; Mercier, Patrick P.; Chandrakasan, Anantha P. | en_US |
| dc.identifier.orcid | https://orcid.org/0000-0002-7820-1625 | |
| dc.identifier.orcid | https://orcid.org/0000-0003-0493-337X | |
| dc.identifier.orcid | https://orcid.org/0000-0002-5977-2748 | |
| mit.license | OPEN_ACCESS_POLICY | en_US |
| mit.metadata.status | Complete | |
