A 3.4-pJ FeRAM-Enabled D Flip-Flop in 0.13-µm CMOS for Nonvolatile Processing in Digital Systems
Author(s)Qazi, Masood; Amerasekera, Ajith; Chandrakasan, Anantha P.
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In order to realize a digital system with no distinction between “on” and “off,” the computational state must be stored in nonvolatile memory elements. If the energy cost and time cost of managing the computational state in nonvolatile memory can be lowered to the microsecond and picojoule-per-bit level, such a system could operate from unreliable harvested energy, never requiring a reboot. This work presents a nonvolatile D-flip-flop (NVDFF) designed in 0.13-μm CMOS that retains state in ferroelectric capacitors during sporadic power loss. The NVDFF is integrated into an ASIC design flow, and a test-case nonvolatile FIR filter with an accompanying power management unit automatically saves and restores the state based on the status of a one-bit indicator of energy availability. Correct operation has been verified over power-cycle intervals from 4.8 μs to 1 day. The round-trip save-restore energy is 3.4 pJ per NVDFF. Also presented are statistical measurements across 21 thinspace000 NVDFFs to validate the capability of the circuit to achieve the requisite 10-ppm failure rate for embedded system applications.
DepartmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
IEEE Journal of Solid-State Circuits
Institute of Electrical and Electronics Engineers (IEEE)
Qazi, Masood, Ajith Amerasekera, and Anantha P. Chandrakasan. “A 3.4-pJ FeRAM-Enabled D Flip-Flop in 0.13-µm CMOS for Nonvolatile Processing in Digital Systems.” IEEE Journal of Solid-State Circuits 49, no. 1 (n.d.): 202–211.