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dc.contributor.authorMarathe, Radhika A.
dc.contributor.authorWang, Wentao
dc.contributor.authorMahmood, Zohaib
dc.contributor.authorDaniel, Luca
dc.contributor.authorWeinstein, Dana
dc.date.accessioned2015-02-06T14:56:28Z
dc.date.available2015-02-06T14:56:28Z
dc.date.issued2012-10
dc.identifier.isbn978-1-4673-2691-9
dc.identifier.isbn978-1-4673-2690-2
dc.identifier.isbn978-1-4673-2689-6
dc.identifier.issn1078-621X
dc.identifier.urihttp://hdl.handle.net/1721.1/93886
dc.description.abstractThis work presents an unreleased CMOS-integrated MEMS resonators fabricated at the transistor level of IBM's 32SOI technology and realized without the need for any post-processing or packaging. These Resonant Body Transistors (RBTs) are driven capacitively and sensed piezoresistively using an n-channel Field Effect Transistor (nFET). Acoustic Bragg Reflectors (ABRs) are used to localize acoustic vibrations in these resonators completely buried in the CMOS stack and surrounded by low-k dielectric. Experimental results from the first generation hybrid CMOS-MEMS show RBTs operating at 11.1-11.5 GHz with footprints <; 5μm × 3μm. The response of active resonators is shown to contrast with passive resonators showing no discernible peak. Comparative behavior of devices with design variations is used to demonstrate the effect of ABRs on spurious mode suppression. Temperature stability and TCF compensation due to complimentary materials in the CMOS stack are experimentally verified.en_US
dc.language.isoen_US
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en_US
dc.relation.isversionofhttp://dx.doi.org/10.1109/SOI.2012.6404400en_US
dc.rightsCreative Commons Attribution-Noncommercial-Share Alikeen_US
dc.rights.urihttp://creativecommons.org/licenses/by-nc-sa/4.0/en_US
dc.sourceProf. Daniel via Chris Sherratten_US
dc.titleResonant Body Transistors in IBM's 32nm SOI CMOS technologyen_US
dc.typeArticleen_US
dc.identifier.citationMarathe, R., W. Wang, Z. Mahmood, L. Daniel, and D. Weinstein. “Resonant Body Transistors in IBM’s 32nm SOI CMOS Technology.” 2012 IEEE International SOI Conference (SOI) (October 2012).en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Scienceen_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Mechanical Engineeringen_US
dc.contributor.approverDaniel, Lucaen_US
dc.contributor.mitauthorMarathe, Radhika A.en_US
dc.contributor.mitauthorWang, Wentaoen_US
dc.contributor.mitauthorMahmood, Zohaiben_US
dc.contributor.mitauthorDaniel, Lucaen_US
dc.contributor.mitauthorWeinstein, Danaen_US
dc.relation.journalProceedings of the 2012 IEEE International SOI Conference (SOI)en_US
dc.eprint.versionAuthor's final manuscripten_US
dc.type.urihttp://purl.org/eprint/type/ConferencePaperen_US
eprint.statushttp://purl.org/eprint/status/NonPeerRevieweden_US
dspace.orderedauthorsMarathe, R.; Wang, W.; Mahmood, Z.; Daniel, L.; Weinstein, D.en_US
dc.identifier.orcidhttps://orcid.org/0000-0002-5880-3151
mit.licenseOPEN_ACCESS_POLICYen_US
mit.metadata.statusComplete


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