Technique for Efficient Evaluation of SRAM Timing Failure
Author(s)Qazi, Masood; Tikekar, Mehul; Dolecek, Lara; Shah, Devavrat; Chandrakasan, Anantha P.
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This brief presents a technique to evaluate the timing variation of static random access memory (SRAM). Specifically, a method called loop flattening, which reduces the evaluation of the timing statistics in the complex highly structured circuit to that of a single chain of component circuits, is justified. Then, to very quickly evaluate the timing delay of a single chain, a statistical method based on importance sampling augmented with targeted high-dimensional spherical sampling can be employed. The overall methodology has shown 650× or greater speedup over the nominal Monte Carlo approach with 10.5% accuracy in probability. Examples based on both the large-signal and small-signal SRAM read path are discussed, and a detailed comparison with state-of-the-art accelerated statistical simulation techniques is given.
DepartmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Institute of Electrical and Electronics Engineers (IEEE)
Qazi, Masood, Mehul Tikekar, Lara Dolecek, Devavrat Shah, and Anantha P. Chandrakasan. “Technique for Efficient Evaluation of SRAM Timing Failure.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21, no. 8 (August 2013): 1558–1562.
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