Cost and Coding Efficient Motion Estimation Design Considerations for High Efficiency Video Coding (HEVC) Standard
Author(s)Sze, Vivienne; Chandrakasan, Anantha P.; Sinangil, M. E.; Zhou, M.
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This paper focuses on motion estimation engine design in future high-efficiency video coding (HEVC) encoders. First, a methodology is explained to analyze hardware implementation cost in terms of hardware area, memory size and memory bandwidth for various possible motion estimation engine designs. For 11 different configurations, hardware cost as well as the coding efficiency are quantified and are compared through a graphical analysis to make design decisions. It has been shown that using smaller block sizes (e.g. 4 × 4) imposes significantly larger hardware requirements at the expense of modest improvements in coding efficiency. Secondly, based on the analysis on various configurations, one configuration is chosen and algorithm improvements are presented to further reduce hardware implementation cost of the selected configuration. Overall, the proposed changes provide 56 × on-chip bandwidth, 151 × off-chip bandwidth, 4.3 × core area and 4.5 × on-chip memory area savings when compared to the hardware implementation of the HM-3.0 design.
DepartmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
IEEE Journal of Selected Topics in Signal Processing
Institute of Electrical and Electronics Engineers (IEEE)
Sinangil, Mahmut E., Vivienne Sze, Minhua Zhou, and Anantha P. Chandrakasan. “Cost and Coding Efficient Motion Estimation Design Considerations for High Efficiency Video Coding (HEVC) Standard.” IEEE J. Sel. Top. Signal Process. 7, no. 6 (December 2013): 1017–1028.
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