dc.contributor.author | Sinangil, Mahmut E. | |
dc.contributor.author | Chandrakasan, Anantha P. | |
dc.date.accessioned | 2015-03-05T19:48:40Z | |
dc.date.available | 2015-03-05T19:48:40Z | |
dc.date.issued | 2013-09 | |
dc.date.submitted | 2013-07 | |
dc.identifier.issn | 0018-9200 | |
dc.identifier.issn | 1558-173X | |
dc.identifier.uri | http://hdl.handle.net/1721.1/95890 | |
dc.description.abstract | This paper presents an application-specific SRAM design targeted towards applications with highly correlated data (e.g., video and imaging applications). A prediction-based reduced bit-line switching activity scheme is proposed to reduce switching activity on the bit-lines based on the proposed bit-cell and array structure. A statistically gated sense-amplifier approach is used to exploit signal statistics on the bit-lines to reduce energy consumption of the sensing network. These techniques provide up to 1.9 × lower energy/access when compared with an 8T SRAM. These savings are in addition to the savings that are achieved through voltage scaling and demonstrate the advantages of an application-specific SRAM design. | en_US |
dc.description.sponsorship | Texas Instruments Incorporated | en_US |
dc.language.iso | en_US | |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en_US |
dc.relation.isversionof | http://dx.doi.org/10.1109/JSSC.2013.2280310 | en_US |
dc.rights | Creative Commons Attribution-Noncommercial-Share Alike | en_US |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-sa/4.0/ | en_US |
dc.source | Chandrakasan | en_US |
dc.title | Application-Specific SRAM Design Using Output Prediction to Reduce Bit-Line Switching Activity and Statistically Gated Sense Amplifiers for Up to 1.9x Lower Energy/Access | en_US |
dc.type | Article | en_US |
dc.identifier.citation | Sinangil, Mahmut E., and Anantha P. Chandrakasan. “Application-Specific SRAM Design Using Output Prediction to Reduce Bit-Line Switching Activity and Statistically Gated Sense Amplifiers for Up to 1.9x Lower Energy/Access.” IEEE Journal of Solid-State Circuits 49, no. 1 (January 2014): 107–117. | en_US |
dc.contributor.department | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science | en_US |
dc.contributor.approver | Chandrakasan, Anantha P. | en_US |
dc.contributor.mitauthor | Chandrakasan, Anantha P. | en_US |
dc.contributor.mitauthor | Sinangil, Mahmut E. | en_US |
dc.relation.journal | IEEE Journal of Solid-State Circuits | en_US |
dc.eprint.version | Author's final manuscript | en_US |
dc.type.uri | http://purl.org/eprint/type/JournalArticle | en_US |
eprint.status | http://purl.org/eprint/status/PeerReviewed | en_US |
dspace.orderedauthors | Sinangil, Mahmut E.; Chandrakasan, Anantha P. | en_US |
dc.identifier.orcid | https://orcid.org/0000-0002-5977-2748 | |
mit.license | OPEN_ACCESS_POLICY | en_US |
mit.metadata.status | Complete | |