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dc.contributor.authorSinangil, Mahmut E.
dc.contributor.authorChandrakasan, Anantha P.
dc.date.accessioned2015-03-05T19:48:40Z
dc.date.available2015-03-05T19:48:40Z
dc.date.issued2013-09
dc.date.submitted2013-07
dc.identifier.issn0018-9200
dc.identifier.issn1558-173X
dc.identifier.urihttp://hdl.handle.net/1721.1/95890
dc.description.abstractThis paper presents an application-specific SRAM design targeted towards applications with highly correlated data (e.g., video and imaging applications). A prediction-based reduced bit-line switching activity scheme is proposed to reduce switching activity on the bit-lines based on the proposed bit-cell and array structure. A statistically gated sense-amplifier approach is used to exploit signal statistics on the bit-lines to reduce energy consumption of the sensing network. These techniques provide up to 1.9 × lower energy/access when compared with an 8T SRAM. These savings are in addition to the savings that are achieved through voltage scaling and demonstrate the advantages of an application-specific SRAM design.en_US
dc.description.sponsorshipTexas Instruments Incorporateden_US
dc.language.isoen_US
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en_US
dc.relation.isversionofhttp://dx.doi.org/10.1109/JSSC.2013.2280310en_US
dc.rightsCreative Commons Attribution-Noncommercial-Share Alikeen_US
dc.rights.urihttp://creativecommons.org/licenses/by-nc-sa/4.0/en_US
dc.sourceChandrakasanen_US
dc.titleApplication-Specific SRAM Design Using Output Prediction to Reduce Bit-Line Switching Activity and Statistically Gated Sense Amplifiers for Up to 1.9x Lower Energy/Accessen_US
dc.typeArticleen_US
dc.identifier.citationSinangil, Mahmut E., and Anantha P. Chandrakasan. “Application-Specific SRAM Design Using Output Prediction to Reduce Bit-Line Switching Activity and Statistically Gated Sense Amplifiers for Up to 1.9x Lower Energy/Access.” IEEE Journal of Solid-State Circuits 49, no. 1 (January 2014): 107–117.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Scienceen_US
dc.contributor.approverChandrakasan, Anantha P.en_US
dc.contributor.mitauthorChandrakasan, Anantha P.en_US
dc.contributor.mitauthorSinangil, Mahmut E.en_US
dc.relation.journalIEEE Journal of Solid-State Circuitsen_US
dc.eprint.versionAuthor's final manuscripten_US
dc.type.urihttp://purl.org/eprint/type/JournalArticleen_US
eprint.statushttp://purl.org/eprint/status/PeerRevieweden_US
dspace.orderedauthorsSinangil, Mahmut E.; Chandrakasan, Anantha P.en_US
dc.identifier.orcidhttps://orcid.org/0000-0002-5977-2748
mit.licenseOPEN_ACCESS_POLICYen_US
mit.metadata.statusComplete


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