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dc.contributor.authorRen, Ling
dc.contributor.authorYu, Xiangyao
dc.contributor.authorVan Dijk, Marten
dc.contributor.authorKhan, Omer
dc.contributor.authorDevadas, Srinivas
dc.contributor.authorFletcher, Christopher Wardlaw
dc.date.accessioned2015-11-23T15:09:04Z
dc.date.available2015-11-23T15:09:04Z
dc.date.issued2014-02
dc.identifier.isbn978-1-4799-3097-5
dc.identifier.urihttp://hdl.handle.net/1721.1/99988
dc.description.abstractOblivious RAM (ORAM) is an established cryptographic technique to hide a program's address pattern to an untrusted storage system. More recently, ORAM schemes have been proposed to replace conventional memory controllers in secure processor settings to protect against information leakage in external memory and the processor I/O bus. A serious problem in current secure processor ORAM proposals is that they don't obfuscate when ORAM accesses are made, or do so in a very conservative manner. Since secure processors make ORAM accesses on last-level cache misses, ORAM access timing strongly correlates to program access pattern (e.g., locality). This brings ORAM's purpose in secure processors into question. This paper makes two contributions. First, we show how a secure processor can bound ORAM timing channel leakage to a user-controllable leakage limit. The secure processor is allowed to dynamically optimize ORAM access rate for power/performance, subject to the constraint that the leakage limit is not violated. Second, we show how changing the leakage limit impacts program efficiency. We present a dynamic scheme that leaks at most 32 bits through the ORAM timing channel and introduces only 20% performance overhead and 12% power overhead relative to a baseline ORAM that has no timing channel protection. By reducing leakage to 16 bits, our scheme degrades in performance by 5% but gains in power efficiency by 3%. We show that a static (zero leakage) scheme imposes a 34% power overhead for equivalent performance (or a 30% performance overhead for equivalent power) relative to our dynamic scheme.en_US
dc.description.sponsorshipUnited States. Dept. of Defense (National Defense Science and Engineering Graduate (NDSEG) Fellowship)en_US
dc.description.sponsorshipUnited States. Defense Advanced Research Projects Agency. Clean-slate Design of Resilient, Adaptive, Secure Hosts (CRASH) Program (Contract N66001-10-2-4089)en_US
dc.language.isoen_US
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en_US
dc.relation.isversionofhttp://dx.doi.org/10.1109/HPCA.2014.6835932en_US
dc.rightsCreative Commons Attribution-Noncommercial-Share Alikeen_US
dc.rights.urihttp://creativecommons.org/licenses/by-nc-sa/4.0/en_US
dc.sourceMIT web domainen_US
dc.titleSuppressing the Oblivious RAM timing channel while making information leakage and program efficiency trade-offsen_US
dc.typeArticleen_US
dc.identifier.citationFletcher, Christopher W., Ling Ren, Xiangyao Yu, Marten Van Dijk, Omer Khan, and Srinivas Devadas. “Suppressing the Oblivious RAM Timing Channel While Making Information Leakage and Program Efficiency Trade-Offs.” 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA) (February 2014).en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Scienceen_US
dc.contributor.mitauthorFletcher, Christopher Wardlawen_US
dc.contributor.mitauthorRen, Lingen_US
dc.contributor.mitauthorYu, Xiangyaoen_US
dc.contributor.mitauthorDevadas, Srinivasen_US
dc.relation.journalProceedings of the 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)en_US
dc.eprint.versionAuthor's final manuscripten_US
dc.type.urihttp://purl.org/eprint/type/ConferencePaperen_US
eprint.statushttp://purl.org/eprint/status/NonPeerRevieweden_US
dspace.orderedauthorsFletchery, Christopher W.; Ren, Ling; Yu, Xiangyao; Van Dijk, Marten; Khan, Omer; Devadas, Srinivasen_US
dc.identifier.orcidhttps://orcid.org/0000-0001-8253-7714
dc.identifier.orcidhttps://orcid.org/0000-0003-3437-7570
dc.identifier.orcidhttps://orcid.org/0000-0003-4317-3457
dc.identifier.orcidhttps://orcid.org/0000-0003-1467-2150
mit.licenseOPEN_ACCESS_POLICYen_US


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