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dc.contributor.authorBiswas, Avishek
dc.contributor.authorSinangil, Yildiz
dc.contributor.authorChandrakasan, Anantha P.
dc.date.accessioned2016-04-20T17:40:37Z
dc.date.available2016-04-20T17:40:37Z
dc.date.issued2014-09
dc.identifier.isbn978-1-4799-5696-8
dc.identifier.isbn978-1-4799-5694-4
dc.identifier.urihttp://hdl.handle.net/1721.1/102279
dc.description.abstractThis paper presents a fully integrated, reconfigurable switched-capacitor based step-up DC-DC converter in a 28nm FDSOI process. Three reconfigurable step-up conversion ratios (5/2, 2/1, 3/2) have been implemented which can provide a wide range of output voltage from 1.2V to 2.4V with a nominal input voltage of 1V. We propose a topology for the 5/2 mode which improves the efficiency by reducing the bottom-plate parasitic loss compared to a conventional series-parallel topology, while delivering the same amount of output power. Further, the proposed topology benefits from using core 1V devices for all charge-transfer switches without incurring any voltage overstress. The converter can deliver load current in the range of 10 μA to 500 μA, achieving a peak efficiency of 88%, using only on-chip MOS and MOM capacitors for a high density implementation.en_US
dc.description.sponsorshipUnited States. Defense Advanced Research Projects Agencyen_US
dc.language.isoen_US
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en_US
dc.relation.isversionofhttp://dx.doi.org/10.1109/ESSCIRC.2014.6942074en_US
dc.rightsCreative Commons Attribution-Noncommercial-Share Alikeen_US
dc.rights.urihttp://creativecommons.org/licenses/by-nc-sa/4.0/en_US
dc.sourceProf. Chandrakasan via Phoebe Ayersen_US
dc.titleA 28nm FDSOI integrated reconfigurable switched-capacitor based step-up DC-DC converter with 88% peak efficiencyen_US
dc.typeArticleen_US
dc.identifier.citationBiswas, Avishek, Yildiz Sinangil, and Anantha P. Chandrakasan. “A 28nm FDSOI Integrated Reconfigurable Switched-Capacitor Based Step-up DC-DC Converter with 88% Peak Efficiency.” ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) (September 2014).en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Scienceen_US
dc.contributor.approverChandrakasan, Anantha P.en_US
dc.contributor.mitauthorBiswas, Avisheken_US
dc.contributor.mitauthorSinangil, Yildizen_US
dc.contributor.mitauthorChandrakasan, Anantha P.en_US
dc.relation.journalProceedings of the 40th European Solid State Circuits Conference (ESSCIRC)en_US
dc.eprint.versionAuthor's final manuscripten_US
dc.type.urihttp://purl.org/eprint/type/ConferencePaperen_US
eprint.statushttp://purl.org/eprint/status/NonPeerRevieweden_US
dspace.orderedauthorsBiswas, Avishek; Sinangil, Yildiz; Chandrakasan, Anantha P.en_US
dc.identifier.orcidhttps://orcid.org/0000-0002-6368-3684
dc.identifier.orcidhttps://orcid.org/0000-0002-5977-2748
mit.licenseOPEN_ACCESS_POLICYen_US


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